Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-08-28
2001-03-27
Etienne, Ario (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S240000
Reexamination Certificate
active
06209053
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of data transfer in a computer system and, more specifically, to a method of operating a multiplexed address and data bus within a computer system to obtain improved data throughput.
BACKGROUND OF THE INVENTION
Communications between devices within a computer system are typically performed using one or more buses that interconnect such devices. These buses may be dedicated buses coupling two devices or non-dedicated buses that are multiplexed by a number of units and devices (i.e. bus agents). Moreover, buses within a computer system may be dedicated to the transfer of a specific type of information. For example, the x86 microprocessor architecture developed by Intel Corporation of Santa Clara, California, includes a three-bus system, with address, data and control buses for respectively transferring address, data and control signals.
In computer systems employing advanced architectures and processors, such as the Pentium Pro® or Pentium II® processors, bus transactions occur in a pipelined manner. Specifically, a next memory access may start after a previous transaction request was issued and all components or phases of a bus transaction are not required to complete before another bus transaction may be initiated. Accordingly, requests from numerous bus agents may be pending at any one time. The pipelining of bus transactions is facilitated by separate data and address buses. While an address of a request is being sent on an address bus, data (or signals) corresponding to an address previously issued on the address bus may be returned on the data bus.
In order to facilitate increased data throughput, computer systems may facilitate burst data transfer, wherein an address is issued on an address bus, and data is returned from the addressed location, as well as a number of immediately subsequent locations as defined, for example, by the Intel burst order scheme. For example, during a burst cache transfer, a full line of data (e.g., 32 bytes) from a cache memory may be placed on a data bus in response to a single address placed on the address bus. In many computer systems, such burst cache transfer may account for a substantial portion activity on buses within the computer system. In these situations, it will be appreciated that the address bus is being under utilized relative to the data bus.
SUMMARY OF THE INVENTION
A method and apparatus for operating a multiplexed address and data bus within a computer system includes the step of arbitrating between an address request and a data request contending for access to the multiplexed bus. This arbitration is performed according to a predetermined criterion. The multiplexed bus is then granted to either the address or data request in accordance with the outcome of the arbitration.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
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Blakely , Sokoloff, Taylor & Zafman LLP
Etienne Ario
Intel Corporation
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