Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-25
2001-08-14
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S653000, C438S654000, C438S656000, C438S685000, C438S692000
Reexamination Certificate
active
06274485
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of polishing a metal layer to form a metal plug without dishing in the manufacture of integrated circuits.
(2) Description of the Prior Art
Tungsten-plug metallization is well-known in the art. A conventional tungsten plug process of the prior art is illustrated in FIG.
1
. Referring now to
FIG. 1
, there is shown semiconductor substrate
10
. A contact, via, or trench is patterned into an oxide layer
20
to an underlying region
11
. A layer of tungsten
26
is deposited which will form a plug within the opening. Typically, barrier metal layer
24
is deposited underlying the tungsten layer
26
. The tungsten and barrier metal layers are then polished using chemical mechanical polishing (CMP) to remove the excess metal material, stopping on the oxide layer, as shown in FIG.
2
. Because of the delayed response time of the oxide endpoint detector, some oxide overpolishing occurs. Since the oxide layer has a lower CMP removal rate than tungsten, the oxide overpolishing will result in dishing
27
of the tungsten plug. In some dense areas of some dies, some of the tungsten and barrier metal is not completely polished away when oxide overpolishing occurs in some other areas. Dishing and tungsten/barrier metal residues remaining after CMP can adversely affect the electrical performance of the integrated circuit device. It is desired to prevent dishing after tungsten CMP and to improve contact resistance between the tungsten plug and the metal stack interconnect.
Co-pending U.S. patent application Ser. No. 09/110,419 to Sudipto R. Roy filed on Jul. 6, 1998 discloses a sacrificial or semi-sacrificial titanium nitride layer deposited over the oxide to protect the oxide and to act as an endpoint detector. Polishing rates of the tungsten and the titanium nitride are comparable, resulting in dishing. U.S. Pat. No. 5,578,523 to Fiordalice et al teaches the use of a polish assisting layer over a dielectric layer and under a metal layer deposited within a trench. The polish assisting layer and the metal layer are polished at close to the same rate in the final stages of polishing, thus preventing dishing. U.S. Pat. No. 5,798,302 to Hudson et al teaches a low friction layer under a metal layer wherein the polishing rate of the low friction layer is much lower than that of the metal layer causing the CMP process to stop at the top surface of the low friction layer. U.S. Pat. No. 5,886,410 to Chiang et al discloses a hard mask over a polymer through which a trench is etched and filled with tungsten. The tungsten is polished with a higher selectivity to tungsten than to the underlying hard mask. U.S. Pat. No. 5,854,140 to Jaso et al teaches a metal stop layer under an aluminum trench filling layer. The aluminum is polished to the stop layer, resulting in dishing. Then the stop layer is removed with a very high selectivity to the stop layer over the aluminum layer so that the resulting aluminum is substantially planar. U.S. Pat. No. 5,776,833 to Chen et al teaches a titanium nitride layer under a tungsten plug layer. CMP stops at the titanium nitride layer. The titanium nitride layer is then removes by etching rather than by polishing resulting in a protruding tungsten plug. U.S. Pat. No. 5,356,513 to Burke et al discloses alternating layers of soft polishing material and hard polish stops to provide tungsten plugs having a substantially planar surface.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of plug metallization including CMP.
Another object of the invention is to provide a method of tungsten plug metallization including CMP.
Yet another object is to provide a method of tungsten plug metallization in which dishing of the plug is prevented.
Yet another object is to provide a method of tungsten plug metallization in which tungsten residues after polishing are eliminated.
A still further object of the invention is to provide a method of plug metallization utilizing a sacrificial high polishing rate layer to prevent dishing of the metal plug.
Another further object of the invention is to provide a method of plug metallization utilizing a sacrificial high polishing rate layer to eliminate metal residues after polishing.
Yet another object of the invention is to provide a method of tungsten plug metallization utilizing a titanium nitride sacrificial high polishing rate layer to prevent dishing of the tungsten plug.
In accordance with the objects of this invention a new method of metal plug metallization utilizing a sacrificial high polishing rate layer to prevent dishing and metal residues after CMP is achieved. An oxide layer is provided overlying semiconductor device structures in and on a semiconductor substrate. A sacrificial high polishing rate (HPR) layer is deposited overlying the oxide layer. An opening is etched through the HPR layer and the oxide layer to one of the semiconductor device structures. A barrier layer and a metal layer are deposited over the surface of the HPR layer and within the opening. The metal layer, barrier layer, and HPR layer overlying the oxide layer are polished away by CMP. The polishing rate of the HPR layer is higher than that of the metal layer with the result that after the HPR layer is completely removed, the metal layer remaining within the opening has a convex shape. The oxide layer is over-polished until endpoint detection is received. Since the metal polishing rate is higher than the oxide polishing rate, the convex shape is made substantially planar during the over-polishing to complete metal plug metallization in the fabrication of an integrated circuit.
REFERENCES:
patent: 5356513 (1994-10-01), Burke et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5763010 (1998-06-01), Guo et al.
patent: 5776833 (1998-07-01), Chen et al.
patent: 5798302 (1998-08-01), Hudson et al.
patent: 5817574 (1998-10-01), Gardner
patent: 5854140 (1998-12-01), Jaso et al.
patent: 5886410 (1999-03-01), Chiang et al.
patent: 6004188 (1999-12-01), Roy
patent: 6051500 (2000-04-01), Maury et al.
patent: 6140224 (2000-10-01), Lin
patent: 6150260 (2000-11-01), Roy
patent: 9-167768 (1997-06-01), None
Chan Lap
Chen Feng
Teo Rick
Bowers Charles
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Smoot Stephen W.
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