Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-09
2001-03-13
Bowers, Charles (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S614000, C438S615000, C438S616000, C438S617000, C438S665000, C438S666000, C438S669000, C438S672000
Reexamination Certificate
active
06200889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention is directed to novel bonding pads for integrated circuit devices for improved reliability, and methods for forming the same.
2. The Relevant Technology
In conventional semiconductor technology, bonding pads are formed in an integrated circuit as part of a top metal layer. The top metal layer is deposited and then patterned to form runners and bonding pads. Passivation layers are then deposited over the top metal layer and patterned, leaving openings in the passivation layers over the bonding pads. Later, during packaging of individual die, each bonding pad has an end of a wire bonded thereto through application of heat, pressure, sonic energy, other forms of energy, or a combination thereof An opposite end of each wire is bonded to an inner portion of a package lead.
The reliability of the bonding process is particularly critical since the bonding process occurs so late in the production cycle. Die being packaged have typically already been tested and sorted. Any problems in the wire bonding process thus impact only good die, and do so only after substantial investment in the production thereof.
Secure, reliable bonding of the wire to the bonding pad requires that the bonding pad be formed of metals compatible with the bonding process. Aluminum and aluminum alloys are typically employed to achieve the most reliable bonds. Reliable bonding further requires a certain minimum bonding pad thickness, so that sufficient material is present to form a secure bond.
An undesirable effect of the current technology is that the above requirements for reliable wire bonding effectively limit the minimum feature size of the top metal layer. Metal layers having sufficient thickness for reliable bonds are typically too thick to be easily patterned at higher resolutions. A relatively thick metal layer requires a relatively thick layer of photoresist to withstand the longer etch required to remove the thick metal layer. But a very high resolution exposure is generally obtained only in conjunction with a shallow depth of focus which is insufficient to provide high resolution exposure throughout a thick photoresist layer. Also, as the aspect ratio of the metal lines increases, the difficulty of adequately cleaning and filling between the lines, resulting in decreasing reliability with increasing thickness. Further, aluminum and aluminum alloys are more susceptible to electromigration than some other metals, which prevents the use of very thin metal lines.
SUMMARY AND OBJECTS OF THE INVENTION
An object of the present invention is to provide improved semiconductor bonding pads for increased bond reliability.
Another object of the present invention is to provide improved semiconductor bonding pads for increased device reliability due to greater resistance of the finished die to mobile ionic contamination.
Another object of the present invention is to provide highly reliable wire bonding pads and a tight pitch top metal level in a single integrated circuit.
Another object of the present invention is to minimize electromigration in a top metal level and maximize wire bond reliability in a single integrated circuit.
Another object of the present invention is to optimize resistivity in a top metal level and optimize wire bond reliability in a single integrated circuit.
Another object of the present invention is to decrease the soft error rate of an integrated circuit.
Another object of the present invention is to improve reliability of the metalization of an integrated circuit by the use of tight pitch single level metalization.
Another object of the present invention is to provide practical and reliable processes for achieving the foregoing objects.
In accordance with a preferred process of the present invention, a top metal layer of an integrated circuit semiconductor wafer is deposited and patterned, with a portion of the resulting top metal layer forming a first bonding pad layer. A first passivation layer is then deposited over the entire surface of the wafer, followed by a second passivation layer. The first and second passivation layers are then patterned, leaving the first bonding pad layers exposed. A bonding pad metal fill layer is then deposited over the entire wafer surface, and then removed over the first and second passivation layers, resulting in top bonding pad layers formed upon the first bonding pad layers.
The resulting inventive bonding pad is thicker than the top metal layer, and extends upward into the openings in the passivation layers, contacting a sidewall of said openings. The top bonding pad layer contacts the second passivation layer, forming therewith over the first passivation layer a barrier against contamination of the first passivation layer, which is typically less resistant to contamination than the second passivation layer. The top bonding pad layer may also have a different composition than the top metal layer, allowing independent optimization of the characteristics of each.
In another preferred process of the present invention, a raised area surrounding location of the bonding pad is provided in the layers underlying the top metal layer. The processing then proceeds as above, but when the bonding pad metal fill layer is removed, only those portions immediately above the raised area are removed, resulting in both a top bonding pad layer upon the first bonding pad layer and a metal radiation shield layer over other areas of the wafer surface.
In accordance with the present invention, one or more intermediate layers may also be employed between the first bonding pad layer and the top bonding pad layer to improve resistivity or other characteristics of the bonding pad.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.
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Bowers Charles
Micro)n Technology, Inc.
Workman & Nydegger & Seeley
Zarneke David A.
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