Copper dendrite prevention by chemical removal of dielectric

Details Copper dendrite prevention by chemical removal of dielectric Copper dendrite prevention by chemical removal of dielectric

1998-11-25

2001-04-17

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S012000, C438S626000, C438S627000, C438S906000

Reexamination Certificate

active

06218290

ABSTRACT:

TECHNICAL FIELD
The present invention relates semiconductor devices comprising copper (Cu) or Cu alloy interconnection patterns. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and reliable high conductivity interconnect structures.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via opening is typically formed by depositing an inter-layer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening in the inter-layer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the inter-layer dielectric is removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves the formation of an opening which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via opening section in communication with an upper trench opening section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Thus, the interconnection pattern limits the speed of the integrated circuit. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the RC delay caused by the interconnect wiring increases. As design rules are reduced to about 0.18 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a replacement material for Al in VLSI interconnection metalizations. Cu is relatively inexpensive, has a lower resistivity than Al, and has improved electrical properties vis-a-vis W. Accordingly, Cu a desirable metal for use as a conductive plug as well as metal wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through the dielectric interlayer, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), and silicon nitride (Si
3
N
4
) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology. For example, conventional practices comprise forming damascene openings in an inter-layer dielectric, depositing a barrier layer, such as TaN, lining the opening and on the surface of the interdielectric layer, and depositing Cu or a Cu alloy layer. CMP is then performed with a slurry, typically an aqueous suspension containing a particulate abrasive, such as alumina, an organic dispersant and an oxidizing agent. CMP is then conducted stopping substantially on the underlying TaN barrier layer. Buffing, employing de-ionized water, is then conducted on a buff pad to remove remaining or residual slurry particles. CMP is then performed employing a more aggressive slurry to remove the underlying TaN barrier layer followed by water buffing on a buff pad to remove residual slurry particles. Subsequent to such CMP procedures, double sided brush scrubbing is typically conducted using water to remove particulate material from the surfaces of the wafer. It was found, however, that such conventional practices left a high level of copper contamination on the surface of the dielectric field adjacent to the Cu or Cu alloy lines, e.g. about 1 to about 2 E
15
atoms/cm
2
of Cu, as detected by TOF (time of flight) SIMS (secondary ion mass spectrometry). This level of Cu contamination in an open field resulted in the growth of dendrites emanating from the edges of Cu or Cu alloy lines into the open dielectric field. Such Cu or Cu compound dendrites typically extend up to about 1 micron and are about 150 Å to about 250 Å thick. Such Cu and Cu compound dendrites reduce the insulating properties of the open dielectric field and can cause shorting by bridging with other Cu or Cu alloy lines.
There exist a need for methodology enabling the formation of reliable Cu and Cu alloy interconnection patterns without the formation of dendrites emanating from Cu or Cu alloy lines.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device comprising highly reliable Cu or Cu alloy interconnects, without dendrites emanating from Cu or Cu alloy lines.
Another advantage of the present invention is a method of preventing dendritic growth from Cu or Cu alloy lines into a bordering open dielectric field.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device on a wafer, the method comprising: forming a copper (Cu) or Cu alloy interconnection pattern comprising a dense array of spaced apart Cu or Cu

Affiliated with

Also associated with

Rating

Copper dendrite prevention by chemical removal of dielectric does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Copper dendrite prevention by chemical removal of dielectric, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Copper dendrite prevention by chemical removal of dielectric will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2481428