Semiconductor device with unbreakable testing elements for...

Details Semiconductor device with unbreakable testing elements for... Semiconductor device with unbreakable testing elements for...

1999-05-17

2001-03-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S014000, C438S017000, C438S241000, C257S308000, C257S311000

Reexamination Certificate

active

06204076

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor device and, more particularly, to a semiconductor device accompanied with testing elements for evaluating components of the semiconductor device and a process of fabrication thereof.
DESCRIPTION OF THE RELATED ART
A typical dynamic random access memory cell is implemented by a series combination of a single field effect transistor and a single storage capacitor. The semiconductor dynamic random access memory device has increased the dynamic random access memory cells, and, accordingly, a real estate occupied by each memory cell is getting narrower and narrower. On the other hand, if the capacitance of the storage capacitor is too small, the data bit stored therein tends to be lost due to the presence of an alpha-particle. For this reason, the manufacturer is required to decrease the occupation area assigned to each dynamic random access memory cell without reduction of the capacitance of the storage capacitor.
One of the approaches is to give a complicated three-dimensional configuration to the storage electrode. This results in increase of the surface area of the storage electrode opposed to the cell plate electrode, and, accordingly, the capacitance is increased without a wide occupation area.
A typical example of the complicated three-dimensional configuration is disclosed in Japanese Patent Publication of Unexamined Application No. 1-270344. The configuration of the storage node electrode is called a “fin structure” or “fin storage node electrode”, and the fin storage node electrode opposes not only the top surface and the side surface but also the back surface to the cell plate, and widely increases the capacitance of the storage capacitor. The fin storage node electrode is located over the associated field effect transistor, and a bit line passes through an inter-level insulating layer between the field effect transistor and the fin storage node electrode. This feature is called a COB (Capacitor-Over-Bit line) structure.
Testing elements are usually incorporated in a semiconductor device, and are used for evaluating components of the semiconductor device. Of course, various testing elements are incorporated in the semiconductor dynamic random access memory device, and some testing elements are used for evaluating the storage node electrode. The manufacturer evaluates a mis-alignment between a node contact hole and a storage node electrode by using one of the testing elements, and measures a sheet resistance of the conductive material for the storage node electrode through another testing element. The manufacturer further checks yet another testing element to see whether or not a short-circuit takes place between adjacent two storage node electrodes.
FIG. 1
illustrates the layout of a typical example of the semiconductor dynamic random access memory device. The prior art semiconductor dynamic random access memory device is fabricated on a p-type silicon substrate
1
. The prior art semiconductor dynamic random access memory device comprises a memory cell array
2
, peripheral circuits such as a row address decoder
3
a
and a column address decoder
3
b
and testing elements
4
a
,
4
b
and
4
c.
A plurality of memory cells
2
a
form the memory cell array
2
, and are arranged in rows and columns. The row address decoder
3
a
selects a row of memory cells
2
a
from the memory cell array
2
, and the column address decoder
3
b
selects a memory cell
2
a
from the selected row of memory cells
2
a.
The memory cell array
2
occupies a central area of the semiconductor substrate
1
, and the peripheral circuits are located in an inner peripheral area around the memory cell array
2
. In this instance, the row address decoder
3
a
extends along one edge of the central area, and the column address decoder
3
b
is provided along another edge of the central area perpendicular to the edge. The testing elements
4
a
to
4
c
are assigned to an outer peripheral area around the inner peripheral area, and are located outside of the peripheral circuits. Thus, the memory cell array
2
, the peripheral circuits
3
a
/
3
b
and the testing elements
4
a
/
4
b
/
4
c
are assigned the central area, the inner peripheral area and the outer peripheral area, respectively.
FIG. 2
illustrates the layout of the memory cell array. A dielectric film and a cell plate electrode are deleted from the layout for the sake of simplicity. One of the memory cells
2
a
is enclosed with broken line BKN, and includes a switching transistor
5
and a stacked type storage capacitor
6
.
An n-type impurity region
1
a
is shaped between two switching transistors
5
of adjacent two memory cells
2
a,
and is electrically connected to a bit line
7
a
through a bit line contact hole
8
a.
The bit line contact holes
8
a
are marked with “x” in
FIG. 2
so as to be easily discriminated.
The half of the n-type impurity region
1
a
on the right side is assigned to the switching transistor
5
for the memory cell
2
a
enclosed with broken line BKN, and a word line
7
b
extends over the half of the n-type impurity region
1
a.
A part of the n-type impurity region
1
a
on the left side of the word line
7
b
and another part of the n-type impurity region
1
a
on the right side of the word line
7
b
serve as a drain region
5
a
and a source region
5
b
of the switching transistor
5
.
The source region
5
b
is electrically connected to a storage node electrode
6
b
through a node contact hole
8
b
also marked with “x”, and the storage node electrode
6
b
is opposed through a dielectric film (not shown in
FIG. 2
) to the cell plate (also not shown in FIG.
2
). The storage node electrode
6
b
is elongated in a direction parallel to the bit line
7
a,
and occupies an area over two word lines
7
b.
The rows
2
b
of memory cells are alternated with the bit lines
7
a,
and the bit lines
7
a
extend in an inter-level insulating layer (not shown in
FIG. 2
) between the word lines
7
b
and the storage node electrodes
6
b
in a perpendicular direction to the word lines
7
b.
The word lines
7
b
are connected to the row address decoder
3
a,
and the bit lines
7
a
are connected to the column address decoder
3
b.
FIGS. 3A
to
3
C illustrate the layouts of the testing elements
4
a,
4
b
and
4
c,
respectively. The manufacturer uses the testing element
4
a
to evaluate the alignment between the node contact holes
8
b
and the stem portions of the storage node electrodes
6
b,
and includes contact holes
4
d
marked with “x” and a polysilicon pattern
4
e
as shown in FIG.
3
A. The contact holes
4
d
are formed in an inter-level insulating layer (not shown in
FIGS. 2 and 3A
) concurrently with the node contact holes
8
b,
and are spaced from each other at predetermined intervals. On the other hand, the polysilicon pattern
4
e
is constituted by a plurality of polysilicon strips
4
f
spaced at the predetermined intervals, and the polysilicon strips
4
f
are patterned from a polysilicon layer concurrently with the storage node electrodes
6
b.
The contact holes
4
d
have a width equal to the width of the storage node electrodes
6
b,
and the length of the contact holes
4
d
is much longer than the length of the storage node electrodes
6
b.
The polysilicon strips
4
f
have a width equal to the width of the storage node electrodes
6
b,
and the length of the polysilicon strips
4
f
is equal to the length of the contact holes
4
d.
Therefore, a mis-alignment between the node contact holes
8
b
and the stems of the storage node electrodes
6
b
is transferred to the alignment between the contact holes
4
d
and the polysilicon strips
4
f.
The manufacturer uses the testing element
4
b
so as to measure the sheet resistance of the polysilicon for the storage node electrodes
6
b.
The testing element
4
b
is implemented by a polysilicon test pattern
4
g,
and a plurality of polysilicon strips
4
h
form in combination the polysilicon test pattern
4
g.
The polysilicon strips
4
h
are patterned from the

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