Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-12
2001-08-28
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S361000
Reexamination Certificate
active
06281553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the technique of a semiconductor device, an electrostatic discharge protection device, and an electrostatic breakdown preventing method, and more specifically, relates to the technique of insulation breakdown of an MOS transistor.
2. Description of the Related Art
In a semiconductor device, especially in an integrated circuit in which the circuit comprises an MOS transistor, a gate insulation breakdown may easily be caused by the electrostatic discharge from the outside to the signal input/output section, and therefore, it is indispensable to provide an electrostatic breakdown protective element to the input/output section.
FIG. 1
is a plan view showing an electrostatic discharge protection device of a conventional semiconductor device described in Japanese patent Application Laid-Open No. 2-238668, and
FIG. 2
is a cross sectional view showing a conventional electrostatic breakdown protective element.
In these figures, numeral
3
denotes a gate electrode,
5
denotes a drain contact,
6
denotes a gate contact,
7
denotes a source contact,
8
denotes a well contact,
9
denotes a p
+
diffusion layer for the connection to a p well,
10
denotes a source,
11
denotes a drain,
12
denotes a p well,
20
denotes an aluminum wiring for connecting the gate electrode to the well,
21
denotes a p
+
diffusion layer for the connection to the well, and
22
denotes a contact hole for connecting the gate electrode to the well. Furthermore,
13
denotes a gate oxide film, and
14
denotes a field oxide film.
In this conventional technique, an internal circuit to be a protected element and an input/output pad are connected to the drain
11
. The gate electrode
3
is connected to the p well
12
by the aluminum wiring
20
, the contact hole
22
, and the p
+
diffusion layer
21
. Furthermore, the p well
12
is connected to the ground electrode by the p
+
diffusion layer
9
.
The action of this electrostatic breakdown protective element will be described. When a high voltage is applied to the drain
11
connected to the input/output pad, a breakdown arises in the junction between the drain
11
and well
12
, and a current flows from the drain
11
to the well
12
, and the internal circuit is protected. Even if the potential of the p well
12
is raised by the current flowing into the p well
12
during the breakdown, the gate electrode
3
is connected to the p well
12
, and the gate electrode
3
and the p well
12
have approximately the same potential, and therefore, it does not occur that the gate insulation film is broken by the difference in potential between the gate electrode
3
and the p well
12
.
However, in the conventional electrostatic discharge protection device, the breakdown in the junction between the diffusion layer and the well is used for the electrostatic protection. The breakdown voltage of the junction depends on the impurity concentration of the junction portion, and generally, it is approximately 8 to 10 V. On the other hand, the gate oxide film of an MOS transistor is broken by an electric field approximately not less than 15 MV/cm, regardless of the film thickness. Therefore, if the gate oxide film is made to be thin by fining of the MOS transistor, the voltage to cause the gate insulation breakdown becomes lower than the breakdown voltage of the junction.
For example, in a gate oxide film having a film thickness of 4 nm, the gate oxide film causes a insulation breakdown at 6 V, and this is clearly a voltage lower than the breakdown voltage of the junction of 8 V. Consequently, in the case where the breakdown of the junction is used for the principle of the action of the protective element, it becomes impossible to protect the internal MOS transistor.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an electrostatic discharge protection device which can prevent the gate insulation breakdown of an internal circuit by acting at a voltage lower than the voltage to cause the gate insulation breakdown, a semiconductor device including this electrostatic discharge protection device, and an electrostatic breakdown preventing method.
The semiconductor device according to the present invention is a device which prevents the gate insulation breakdown by an electrostatic discharge from the outside to the signal input/output section of an integrated circuit including an MOS transistor. This semiconductor device is arranged such that the contact area of the well contact hole to the well is limited by the gate electrode provided in the contact hole area so that the connection resistance to the well may be raised.
In that case, it is preferable to set the connection resistance of the contact hole to the well at a resistance value at which the parasitic bipolar transistor of the MOS transistor can be made to be in the on state at a voltage not more than the voltage to cause a gate insulation breakdown.
Furthermore, another semiconductor device according to the present invention, comprises:
a well of one conductive type which is formed on the surface layer portion in a semiconductor substrate of one conductive type and has an impurity concentration higher than that of the semiconductor substrate;
a source and a drain of the opposite conductive type which are formed on the surface layer portion in the well of one conductive type and are separated by a channel area;
a well contact area of one conductive type which is formed on the surface layer portion in the well of one conductive type and is separated from the source and drain by a field insulation film;
a contact hole which is formed in the surface of the semiconductor substrate and connects the metal wiring on the well contact area and the well contact area;
a gate electrode which is formed on the channel area through the gate insulation film to the surface of the semiconductor substrate; and
a gate electrode which is formed in the well contact hole area through the gate insulation film to the surface of the semiconductor substrate.
Then, the drain is connected to the input/output wiring, and said source, gate electrode, and well contact are connected to the ground potential or the source potential as source wiring.
In that case, such an arrangement that the contact area to the well of one conductive type is limited by the gate electrode formed in the well contact hole area, is also possible.
Furthermore, such an arrangement that the contact area to the well of one conductive type is limited by arranging the gate electrodes formed in the well contact hole area on both sides of the well contact, is also possible.
Furthermore, such an arrangement that the contact area to the well of one conductive type is limited by arranging the gate electrodes formed in the well contact hole area, in the form of surrounding the periphery of the well contact, is also possible.
Furthermore, such an arrangement that the contact area to the well of one conductive type is limited by arranging the gate electrode formed in the well contact hole area, in the central portion of the well contact, is also possible.
Moreover, such an arrangement that the contact area to the well of one conductive type is limited by connecting the gate electrode formed in the well contact hole area, to the gate electrode formed on the channel area, is also possible.
Furthermore, the electrostatic discharge protection device of the present invention is an electrostatic discharge protection device of a semiconductor device including an MOS transistor, in which the source, gate, and well are connected to the ground potential or the source potential of the source wiring and the drain is connected to the input/output wiring. This electrostatic discharge protection device includes such a function that the contact area of the well contact hole to the well is limited by the gate electrode insulated from the well with the gate insulation film provided in the well contact area, and that the action of the parasitic bipolar transistor of
NEC Corporation
Prenty Mark V.
Young & Thompson
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