Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-02-07
2001-04-10
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
Reexamination Certificate
active
06215721
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-bank semiconductor memory device and a method for arranging input and output (I/O) lines. More particularly, the invention relates to an improved architecture leading to efficiency in chip manufacture and design.
2. Description of the Related Art
A semiconductor memory device may employ different architecture such as multi-bit architecture or multi-bank architecture to enhance performance. In multi-memory bank architecture, memory banks can be readily accessed independently and selectively by a bank address method.
In such a multi-memory bank architecture, a write operation, a read operation, and an interrupt operation can be performed in different memory banks. The multi-memory bank architecture includes a bank data bus, which may be a global I/O line, carrying the data read from each memory bank and the data to be written.
Further, each memory bank is divided into a plurality of memory blocks according to the increasing number of memory cells included in one memory bank. The plurality of memory blocks are connected to global I/O lines through a plurality of local I/O lines. Accordingly, each memory block should include sense amplifier blocks, word-line driving blocks, sense amplifier driving circuits, and line transfer circuits because each memory bank is divided into a plurality of memory blocks.
The above-described multi-memory bank architecture is disclosed in U.S. Pat. No. 5,781,495. Specifically, the disclosed architecture includes a plurality of global I/O line pairs passing through the upper side of a memory cell array and extended across a plurality of memory banks.
The efficiency of such multi-memory bank architecture suffers however due to the added size.
Therefore a need exists for a multi-memory bank architecture to improve cell efficiency and chip efficiency.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a multi-bank semiconductor memory device and a method for arranging I/O lines for improving chip efficiency by dividing a plurality of memory banks with I/O sense amplifier blocks.
Another object of the present invention is to provide a multi-bank semiconductor memory device and a method for arranging I/O lines which increases the efficiency of chip manufacture and design by alternately disposing I/O line transfer transistors and sense amplifier driving transistors.
Still another object of the present invention is to provide a multi-bank semiconductor memory device and a method for arranging I/O lines for ease of bank addressing by crossing global I/O line pairs.
Another object of the present invention is to provide a multi-bank semiconductor memory device and a method for arranging I/O lines to increase chip operating speed through an equalizing operation of global I/O line pairs in a write-interrupt-read mode.
To accomplish the above-mentioned objects, a device of the present invention comprises: a plurality of memory banks arranged in the direction of a row; an I/O sense amplifier block which is disposed between adjacent pairs of a plurality of the memory banks, and which includes a plurality of I/O sense amplifiers arranged in the direction of a column; a plurality of column-decoder blocks disposed between each adjacent pair of the memory banks; a plurality of local I/O line pairs extended in each of the memory banks through each memory block therein, in the direction of a column; a plurality of global I/O line pairs, which are extended in one memory bank of each adjacent pair of the memory banks in the direction of a row, which intersect each other on each column-decoder block, and which are extended in the other memory bank in the direction of the other row in the word-line driving block previously containing the intersecting global I/O line pairs.
Each pair of local I/O line pair is preferably disposed on a plurality of sense amplifier block columns arranged in each memory bank in the direction of a row. A pair of local I/O line pair is disposed on each sense amplifier block column. Each pair of the global I/O line pair is disposed on a plurality of word-line driving block rows, the word-line driving blocks are arranged in each memory bank in the direction of a column. A pair of the global I/O lines is disposed at each of the word-line driving block rows. Each of the global I/O line pair is connected with the local I/O line pair crossed at the identical word-line driving block row by having an identical address. In memory banks where global I/O line pairs are not connected with the local I/O line pairs, the global I/O line pair is disposed on adjacent word-line driving block rows. The sense amplifier block columns and sense amplifier driving circuit blocks are disposed in the region of word-line driving block rows where the global I/O line pairs are not connected to the local I/O line pairs. Each of the plurality of global I/O line pairs includes a plurality of equalizer means, which are connected to an end point, and middle points between each memory bank and column-decoder. A plurality of the equalizer means perform an equalizing operation in a write-interrupt-read mode.
According to the present invention, a method for arranging I/O lines of a multi-bank semiconductor memory device having a plurality of I/O sense amplifiers in the direction of a column between adjacent pairs of a plurality of memory banks arranged in the direction of a row, comprises the following steps of: arranging a plurality of local I/O line pairs in the direction of a row, which are extended in each memory bank in the direction of a column, having a column-decoder disposed between each adjacent memory bank in a memory area; and arranging a plurality of global I/O line pairs, which are extended in one memory bank of each adjacent pair of the memory banks in the direction of a row, which intersect each other on each column-decoder block, and which are extended in the other memory bank in the direction of the other row in the word-line driving block previously containing the intersecting global I/O line pairs.
Wherein, it is preferred that each of the plurality of global I/O line pair includes a plurality of equalizer means which are connected to an end point, and middle points between each memory bank and column-decoder. The plurality of equalizer means perform an equalizing operation in a write-interrupt-read mode.
Also, a device of the present invention comprises: a pair of element formation areas divided on a semiconductor wafer; a peripheral circuit area disposed on the center of the element formation area for dividing each element formation area into a pair of sub-element formation areas; an input/output sense amplifier block disposed on the center of the sub-element formation area for dividing each sub-element formation area into a pair of memory areas; a column-decoder block disposed on the center of the memory area for dividing each memory area into a pair of memory banks; and a plurality of global I/O line pairs.
Wherein, a first pair of global I/O line pair is extended in a memory bank adjacent to an I/O sense amplifier block in the direction of a first row. A second pair of global I/O line pair is extended in the direction of a second row adjacent to the first row. The four global I/O line pair intersect each other on the column-decoder block. The first pair of global I/O line pair is extended on other memory bank adjacent to the column-decoder in the direction of the second row. The second pair of global I/O line pair is extended in the first row. The global I/O line pairs are repeatedly disposed in the direction of a column.
Global I/O line pairs are connected to I/O sense amplifiers different from each other, respectively. The first pair of global I/O line pair of the intersecting global I/O line pairs are connected to local I/O line pairs in a first memory bank. The second pair of global I/O line pair of the intersecting global I/O line pairs are connected to local I/O lines pairs in a second memory bank. Global I/O line pair connect to local I/
F. Chau & Associates LLP
Phan Trong
Samsung Electronics Co,. Ltd.
LandOfFree
Multi-bank memory device and method for arranging... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-bank memory device and method for arranging..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-bank memory device and method for arranging... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2479774