Methods of forming SOI insulator layers, methods of forming...

Details Methods of forming SOI insulator layers, methods of forming... Methods of forming SOI insulator layers, methods of forming...

2000-10-03

2001-08-21

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S166000, C438S466000

Reexamination Certificate

active

06277680

ABSTRACT:

TECHNICAL FIELD
The invention pertains to methods of forming silicon-on-insulator layers, methods of forming transistor devices, and to semiconductor devices and assemblies.
BACKGROUND OF THE INVENTION
Numerous semiconductor devices and assemblies may be formed utilizing silicon-on-insulator (SOI) constructions. Such assemblies can include, for example, fully depleted SOI devices or partially-deleted SOI devices. Among SOI devices are n-channel transistors and p-channel transistors. Such transistors can, depending on the desired characteristics, be either fully depleted SOI devices or partially depleted SOI devices. Also, such transistors can be incorporated into specific types of devices, such as, for example, memory array transistor devices and peripheral transistor devices.
There are generally two ways of providing a starting substrate for SOI fabrication. In a first method, oxygen is implanted at a desired depth into a silicon wafer. The wafer is then subjected to an anneal to form a buried silicon dioxide layer having an outward monocrystalline silicon layer thereover. The anneal can also repair damage caused by the implant, although the repair is typically not perfect.
In a second method, a silicon wafer is initially provided with an outer silicon dioxide layer. Such outer silicon dioxide layer can be formed, for example, by exposing the wafer to an oxidizing ambient. After formation of the outer silicon dioxide layer, a separate silicon wafer is positioned against the silicon dioxide layer to form a composite comprising the silicon dioxide layer sandwiched between a pair of silicon wafers. The composite is heated in a furnace to cause fusing of the silicon wafers with the silicon dioxide. Thereafter, the second silicon wafer is mechanically polished down to a desired thickness such that its remnants constitute an SOI construction.
In many applications, it is desired to have an SOI construction in which the silicon layer has a substantially uniform thickness throughout its construction. A method for improving the uniformity of thickness of a silicon layer in an SOI construction is described with reference to
FIG. 1
, which illustrates an apparatus
10
configured for electrostatically etching a silicon layer of a SOI construction. Apparatus
10
comprises a vessel
12
within which is an etching composition
14
preferably comprising potassium hydroxide. A heater
16
is provided within etching composition
14
to control a temperature of the composition during an etching process. An SOI construction
18
is supported within vessel
12
by a TEFLON™ holder
20
which comprises a back support
22
and a front support
24
. SOI construction
18
is compressed between back support
22
and front support
24
. A first O-ring
26
is between SOI construction
18
and front support
24
and seals a back of SOI construction
18
from exposure to etching composition
14
. A second O-ring
34
seals front support
24
against back support
22
. An electrode
28
extends across a back of SOI construction
18
and supports the back of SOI construction
18
while also providing an electrical connection to SOI construction
18
. Electrode
28
is electrically connected through a voltage supply
30
to a platinum electrode
32
extending within etching composition
14
.
An expanded view of zone
2
of
FIG. 1
is shown in FIG.
2
. As shown, SOI construction
18
comprises a substrate portion
40
, an insulator layer
42
, and a silicon layer
44
. Silicon layer
44
is a “frontside” of construction
18
and substrate
40
is a “backside” of construction
18
. Frontside
44
is exposed to etching composition
14
.
In operation, silicon layer
44
is generally lightly doped, with, for example, a p-type conductivity-enhancing dopant. A voltage is provided with voltage supply
30
to force a depletion region
46
to be formed within silicon layer
44
. Etching composition
14
then etches silicon layer
44
to about depletion region
46
and stops. A thickness of depletion region
46
can be controlled by controlling a voltage provided by voltage supply
30
. Although it is not clear if the etching composition stops etching at the depletion layer, or at some location near the depletion layer, it is clear that the amount of silicon etched from layer
44
can be controlled by controlling a thickness of depletion layer
46
.
In operation, a 20% (wt) potassium hydroxide solution is typically used as an etchant and 50-75 volts are applied by voltage supply
30
for a typical etching duration of about six minutes. The temperature of the potassium hydroxide solution is typically controlled to be about 70° C. with temperature controller
16
.
The above-discussed methods of forming SOI constructions are utilized to form constructions in which the silicon layer has a relatively uniform thickness. However, in accordance with the invention which follows it is recognized that there may be some applications in which it is desirable to form SOI constructions having a silicon layer of varying thickness. Accordingly, methods are described for creating SOI constructions in which the silicon layer has a varying thickness. Also described are assemblies and devices designed to take advantage of an SOI construction within which the silicon layer has a varied thickness.
SUMMARY OF THE INVENTION
The invention encompasses methods of forming SOI constructions having varying thicknesses within the silicon layer. The invention also encompasses methods of forming transistor devices from such SOI constructions. Additionally, the invention encompasses semiconductor devices and assemblies utilizing SOI constructions which have varying thicknesses of the silicon layer.
In one aspect, the invention encompasses a method of forming a semiconductor-on-insulator layer wherein a substrate is provided, an insulator layer is provided over the substrate and a semiconductive layer is provided over the insulator layer. The semiconductive layer has a first portion and a second portion. A depletion region is formed within the semiconductive layer proximate the insulator layer. A thickness of the depletion region is controlled to form a different thickness in the first portion than in the second portion. The semiconductive layer is etched to about the depletion region.
In another aspect, the invention encompasses a method of forming a semiconductor-on-insulator layer wherein a semiconductive substrate is provided. The semiconductive substrate has a substantially uniform doping with a first impurity. A first portion of the semiconductive substrate is doped with a second impurity. A second portion of the semiconductive substrate is doped with a third impurity. A third portion of the semiconductive substrate is left undoped with either of the second impurity or the third impurity. An insulator layer is formed over the semiconductive substrate. A semiconductive layer is formed over the insulator layer. The semiconductive layer is substantially uniformly doped with a p-type impurity. A depletion region is formed within the semiconductive layer. The depletion region is formed over the first portion, the second portion and the third portion. The depletion region is thicker over the first portion of the substrate relative to over the second and third portions. The depletion region is thinner over the second portion of the substrate relative to over the first and third portions. The semiconductive layer is exposed to an electrolytic etching composition to etch the semiconductive layer to about the depletion region.
In another aspect, the invention encompasses a method of forming a thin film transistor wherein a substrate is provided. A source template portion, a channel template portion and a drain template portion of the substrate are defined. The source and drain template portions are doped differently than the channel template portion. An insulator layer is formed over the substrate. A semiconductive layer is formed over the insulator layer. A depletion region is formed within the semiconductive layer. The depletion region is over the so

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