Method of forming an integrated circuit package at a wafer...

Details Method of forming an integrated circuit package at a wafer... Method of forming an integrated circuit package at a wafer...

2000-04-25

2001-08-28

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S108000, C438S615000, C438S616000, C257S738000, C257S778000

Reexamination Certificate

active

06281046

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to integrated circuit packages, and more specifically to a method of forming a ball-grid array integrated package at a wafer level.
BACKGROUND ART
The footprint of an integrated circuit package on a circuit board is the area of the board occupied by the package. It is generally desired to minimize the footprint and to place packages close together. In recent years, the ball-grid array (BGA) package has emerged as one of the more popular package types because it provides high density, minimum footprint, and shorter electrical paths, which means that it has better performance than previous types of semiconductor packages.
A typical BGA package is shown in FIG.
10
. In the BGA package
110
, an integrated circuit chip
122
is mounted by means of a bonding layer on an upper surface of a base
112
made of a substrate material. Metal bonding wires or wirebond leads
120
electrically connect a plurality of metal chip pads
126
formed on the upper surface of the chip
122
with wire bonding pads
128
formed on the upper surface of the base
112
. The base
112
includes plated through-hole vias
118
and metal traces
114
to connect the circuitry from the upper surface to the lower surface of the base
112
. A plurality of solder balls
116
are placed on the bottom surface of the base
112
and are electrically connected to the metal traces
114
of the base. The solder balls
116
can be arranged in a uniform full matrix array over the entire bottom surface, in a staggered full array, or around the perimeter of the bottom surface in multiple rows. The solder balls are then used to mechanically and electrically secure the chip package onto a printed circuit board in the end-use product.
While the BGA packages of the prior art provide a great improvement over earlier types of packages in terms of high density and high I/O capability, it is always desired to make the IC package even smaller to further decrease the amount of space needed on a printed circuit board to accommodate the package. Because the wirebond leads are of a predetermined length and require a minimum spacing between adjacent bonding sites to provide sufficient room for the bonding tool, the substrate base must be larger than the chip and it is not possible to fabricate a more compact package. Ideally, it is desired to make a package in which the substrate base does not have to be any larger than the size of the chip.
In the prior art, as described above, it is common to fabricate a package for each individual die. Others have realized that it would be advantageous to be able to form the IC package at the wafer level, that is, after the individual chips have been formed on the wafer but before the wafer has been diced into individual chips. This allows for easier mass production of chip packages and for several chip packages, arranged in a matrix format on the wafer, to be manufactured and tested all at one time. This can reduce time and cost in the process of packaging and testing IC chips.
Some examples of packaging methods in the prior art that are conducted at the wafer level include: U.S. Pat. No. 5,604,160 to Warfield, which discloses using a cap wafer to package semiconductor devices on a device wafer; U.S. Pat. No. 5,798,557 to Salatino et al., which describes a wafer level hermetically packaged integrated circuit having a protective cover wafer bonded to a semiconductor device substrate wafer; and U.S. Pat. No. 5,851,845 to Wood et al., which discloses a method of forming a semiconductor package by providing a wafer containing a plurality of dice, thinning a backside of the wafer by polishing or etching, attaching the thinned wafer to a substrate, and then dicing the wafer.
It is the object of the present invention to provide a ball-grid array IC package that has a minimum size such that the IC package takes up no more space than the area of the IC chip.
It is a further object of the invention to provide a method of forming such an IC package at the wafer level in order to take advantage of the greater efficiency in mass production and the ability to conduct parallel testing of the IC packages.
SUMMARY OF THE INVENTION
The above objects have been achieved in a method of forming an integrated circuit package on the wafer level using a flip chip design with a single wafer. The integrated circuit package is formed by first providing a product silicon wafer having a plurality of microelectric circuits fabricated thereon and having a plurality of standard aluminum bonding pads exposed. The aluminum bonding pads are re-metallized to be solderable. Then, a plurality of solder bumps are deposited on the bonding pad sites. Then, a layer of underfill-flux material is deposited onto the wafer surface, over the solder bumps. A pre-fabricated interposer substrate, having metallized through-holes, is aligned to the wafer and then the assembly is reflowed, or cured, to secure the interposer substrate to the layer of underfill-flux material, and to form the electrical connection between the circuitry on the substrate and the bonding pads on the silicon wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are then reflowed forming a BGA structure. The wafer is then diced and the individual BGA packages are formed. The BGA package is ready for the next level assembly.
The integrated circuit package of the present invention is smaller than BGA packages of the prior art in that the additional space usually required because of the use of wirebonding leads is not necessary. The whole wafer can be packaged all at one time which is more efficient than packaging each die individually and allows for parallel testing of the packaged dice while still in wafer form. Additionally, the method of the present invention is easy to implement because, since the solder bumps are defined first, there is no need to be concerned with keeping the bonding pads clean for later addition of solder during the step of adding the adhesive (underfill-flux) layer. Also, since the solder bumps are already in place, it makes it easier to align the solder bumps to the plated through-holes of the interposer substrate.


REFERENCES:
patent: 5569963 (1996-10-01), Rostoker et al.
patent: 5604160 (1997-02-01), Warfield
patent: 5798557 (1998-08-01), Salatino et al.
patent: 5821624 (1998-10-01), Pasch
patent: 5851845 (1998-12-01), Wood et al.
patent: 6004867 (1999-12-01), Kim et al.
patent: 6020637 (2000-02-01), Karnezos

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