Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-02-29
2001-03-27
Lee, Eddie C. (Department: 2815)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S783000, C438S784000, C438S778000
Reexamination Certificate
active
06207589
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates generally to integrated circuit (IC) fabrication processes and, more particularly, to a high dielectric constant gate insulation film, and a deposition method for such film.
Current Si VLSI technology uses SiO
2
as the gate dielectric in MOS devices. As device dimensions continue to scale down, the thickness of the SiO
2
layer must also decrease to maintain the same capacitance between the gate and channel regions. Thicknesses of less than 2 nanometers (nm) are expected in the future. However, the occurrence of high tunneling current through such thin layers of SiO
2
requires that alternate materials be considered. Materials with high dielectric constants would permit gate dielectric layers to be made thicker, and so alleviate the tunneling current problem. These so-called high-k dielectric films are defined herein as having a high dielectric constant relative to silicon dioxide. Typically, silicon dioxide has a dielectric constant of approximately 4, while high-k films have a dielectric constant of greater than approximately 10. Current high-k candidate materials include titanium oxide (TiO
2
), zirconium oxide (ZrO
2
), tantalum oxide (Ta
2
O
5
), and barium and strontium titanium oxide (Ba,Sr)TiO
3
.
One common problem associated with the above-mentioned high-k dielectrics is that they develop a crystalline structure under normal preparation conditions. As a result, the surface of the film is very rough. Surface roughness causes non-uniform electrical fields in the channel region adjacent the dielectric film. Such films are not suitable for the gate dielectrics of MOSFET devices.
Because of high direct tunneling currents, SiO
2
films thinner than 1.5 nm cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts in the search for the replacement of SiO
2
, with TiO
2
and Ta
2
O
5
attracting the greatest attention. However, high temperature post deposition annealing, and the formation of an interfacial SiO
2
layer, make achieving equivalent SiO
2
thicknesses (EOT) of less than 1.5 nm very difficult.
It would be advantageous if a high-k dielectric film could be used as an insulating barrier between a gate electrode and the underlying channel region in a MOS transistor.
It would be advantageous if high-k dielectric films could be formed with reduced surface roughness, crystallinity, and electrical leakage. It would be advantageous if these non-crystalline high dielectric constant materials could be used in gate dielectrics and storage capacitors of integrated circuits.
It would be advantageous if improved high-k dielectric materials could be formed by simply doping, or otherwise adding additional elements to currently existing high-k dielectric materials.
Accordingly, a thin film having a high dielectric constant (10 to 25) is provided. The film including a trivalent metal, such as aluminum (Al), scandium (Sc), or lanthanum (La), a metal selected from the group consisting of zirconium (Zr) and hafnium (Hf), and oxygen.
Typically, the percentage of trivalent metal in the film does not exceed approximately 50%, with Al at a percentage of approximately 25% being preferred.
Also provided is a MOSFET transistor. The transistor comprising a gate electrode, a channel region having a top surface underlying said gate electrode, and a gate dielectric film interposed between the gate electrode and the channel region top surface. The content of the dielectric film is as described above. Typically, the gate dielectric film has a thickness in the range of approximately 20 and 200 Å.
Some aspects of the invention further comprise the transistor having an interface barrier, with a thickness in the range of approximately 2 to 5 Å, interposed between the channel region and the gate dielectric film. The interface materials are selected from the group consisting of silicon nitride and silicon oxynitride, whereby the channel region top surface is made smoother to prevent the degradation of electron mobility of the MOSFET.
In the fabrication of an integrated circuit (IC) having a surface, a sputtering method is also provided to form a doped metal oxide film on the IC surface. The method comprises the steps of:
a) establishing an atmosphere including oxygen;
b) sputtering at least one target metal including a metal selected from the group consisting of Zr and Hf, and including a trivalent metal on the IC silicon surface;
c) in response to Steps a) and b), forming the doped metal oxide film; and
d) annealing at a temperature in the range of approximately 400 and 800 degrees C, whereby a thin film having a high dielectric constant and good insulating properties is formed.
In some aspects of the invention Step a) includes co-sputtering with separate targets including a first target of a metal selected from the group consisting of Zr and Hf, and a second target including a trivalent metal.
Alternately, a chemical vapor deposition (CVD) method of depositing the doped metal oxide film is provided comprising the steps of:
a) preparing at least one precursor including a metal selected from the group consisting of Zr and Hf, and a trivalent metal;
b) vaporizing the precursor;
c) establishing an atmosphere including oxygen;
d) decomposing the precursor on the IC surface to deposit, by chemical vapor deposition (CVD), an alloy film including a metal selected from the group consisting of Zr and Hf, a trivalent metal, and oxygen; and
e) annealing at a temperature in the range of approximately 400 to 800 degrees C, whereby a thin film having a high dielectric constant and good barrier properties is formed.
In yet another alternate, an evaporation deposition method of depositing the doped metal oxide film is provided comprising the steps of:
a) establishing a vacuum (gas-free) atmosphere;
b) preparing at least one crucible including a metal selected from the group consisting of Zr and Hf, and a trivalent metal;
c) heating the at least one crucible at a temperature in the range of approximately 1000 and 2000 degrees C, to evaporate the metals prepared in Step b);
d) in response to Steps a) through c), depositing an alloy film including a metal selected from the group consisting of Zr and Hf, and a trivalent metal; and
e) annealing in an atmosphere including oxygen at a temperature in the range of approximately 400 to 800 degrees C, to form an alloy film with oxygen, whereby a thin film having a high dielectric constant and good barrier properties is formed.
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Ma Yanjun
Ono Yoshi
Krieger Scott C.
Lee Eddie C.
Rabdau Matthew D.
Richards N. Drew
Ripma David C.
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