Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-01
2001-06-19
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S365000, C257S773000, C257S775000
Reexamination Certificate
active
06249032
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to semiconductor devices and, more particularly, to a semiconductor device having patterned metal layer over a polysilicon line and a method of forming such a semiconductor device.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG.
1
. The device generally includes a semiconductor substrate
101
on which a gate electrode
103
is disposed. The gate electrode
103
is typically a polysilicon line which acts as a conductor. An input signal is typically applied to the gate electrode
103
via a gate terminal (not shown). Heavily-doped source/drain regions
105
are formed in the semiconductor substrate
101
and are connected to source/drain terminals (not shown). The source/drain regions
105
may, for example, be lightly-doped drain (LDD) source/drain regions as shown. As illustrated in
FIG. 1
, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region
107
is formed in the semiconductor substrate
101
beneath the gate electrode
103
and separates the source/drain regions
105
. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions
105
. The gate electrode
103
is generally separated from the semiconductor substrate
101
by an insulating layer
109
, typically an oxide layer such as SiO2. The insulating layer
109
is provided to prevent current from flowing between the gate electrode
103
and the source/drain regions
105
or channel region
107
.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode
103
, a transverse electric field is set up in the channel region
107
. By varying the transverse electric field, it is possible to modulate the conductance of the channel region
107
between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region
107
. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
In a completed device structure, the source/drain regions
105
and gate electrode
103
(as well as other types of polysilicon lines) are typically contacted by metal contacts in order to interconnect these structures with other elements of the device. Prior to forming the metal contacts, silicidation layers
111
are typically formed over the source/drain regions
105
and the gate electrode
103
. The silicidation layers
111
are typically formed by depositing a layer of metal, such as tungsten or cobalt, over the substrate
101
and annealing the wafer. During the annealing process, the deposited metal reacts with the underlying silicon substrate and polysilicon gate electrode to form the silicidation layers
111
. The silicidation layers
111
facilitate contact between the metal contacts and the source/drain regions
105
and the gate electrode
103
and also lower the sheet resistance of the source/drain regions
105
and the gate electrode
103
.
Semiconductor devices, like the one described above, are used in large numbers to construct most modem electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). To accomplish these goals, it is desirable to reduce the size of the semiconductor devices without degrading their performance.
As the device is made smaller fabrication complexity typically increases and conventional techniques for fabricating semiconductor devices may give rise to new problems. For instance, conventionally formed silicide layers on small-scale gate electrodes (e.g., 0.18 microns or less) typically have higher sheet resistances than similar silicides on larger gate electrodes. The increase in sheet resistance typically has a significant deleterious impact on device performance. In addition, the narrow width of small scale gate electrodes presents significant contact problems. New semiconductor fabrication processes and devices are there needed to continue the trend of reduced semiconductor device size and increased performance.
SUMMARY OF THE INVENTION
Generally, the present invention relates to a semiconductor device having at least one polysilicon line having an extended patterned metal layer and a method of fabricating such as device.
In one embodiment of the invention, a polysilicon line is formed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is forming over the substrate and adjacent the polysilicon line and a patterned metal layer having a greater width than the polysilicon line is formed over the polysilicon line. A dielectric layer is then formed over the patterned metal layer and a contact is formed to the patterned metal layer.
In another embodiment of the invention, a process of forming a semiconductor device is provided in which first and second polysilicon lines are formed on a substrate and a dielectric layer is formed adjacent the first and second polysilicon lines. Next, there is formed a patterned metal layer including first and second metal lines each disposed over a respective first and second polysilicon lines and each having a greater width than the respective polysilicon line. The patterned metal layer further includes a portion connecting the first and second metal lines. A dielectric layer is then formed over the patterned metal layer and a contact is formed in the dielectric layer to the patterned metal layer.
A semiconductor device, in accordance with one embodiment of the invention, includes a substrate, at least one polysilicon line disposed over the substrate, and a patterned metal layer having a greater width than the polysilicon line is disposed on top of the polysilicon line. The patterned metal layer includes an edge which extends beyond an edge of the polysilicon line by 10% or more of the polysilicon line width. The polysilicon line may, for example, be a gate electrode. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A dielectric layer may be disposed over the patterned metal layer and a contact to the patterned metal layer may be formed in the dielectric layer.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5614762 (1997-03-01), Kanamori et al.
patent: 5675187 (1997-10-01), Numata et al.
patent: 5719429 (1998-02-01), Yoshida et al.
patent: 5900668 (1999-05-01), Wollesen
Fulford H. Jim
May Charles E.
Nariman Homi E.
Advanced Micro Devices , Inc.
Baumeister Bradley WM.
Lee Eddie C.
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