Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-10
2001-05-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S421000, C438S422000, C438S428000, C438S595000, C438S632000, C438S760000
Reexamination Certificate
active
06228756
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing an inter-metal dielectric layer. More particularly, the present invention relates to a method of manufacturing an inter-metal layer which can decrease the resistor-capacitor time delay (RC time delay) in a device.
2. Description of Related Art
In the process for manufacturing an ultra large-scale integrated circuit, more than a hundred thousand transistors are located on a silicon substrate within an area of about 1-2 square centimeters. Additionally, in order to increase the integration of the integrated circuits (ICs), the density of wires used to electrically couple the transistors to each other or the other devices to each other is increased. Therefore, in accord with the increased interconnect manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two metal layers. In particular, a number of function-complicated products, such as microprocessors, even require 4 or 5 metal layers to complete the internal connections. Generally, an inter-metal dielectric (IMD) layer is used to electrically isolate two adjacent metal layers from each other. Moreover, a conductive layer used to electrically connect the two adjacent metal layers is called a via plug in the semiconductor industry.
However, due to the increasingly high integration of ICs, the distance between the adjacent wires is decreased. If the dielectric constant of the IMD layer used an electrically isolating material between the wires can not be efficiently decreased, the rate of data transmission between the devices is decreased due to the increasing of the RC time delay. Hence, the ability of the devices is limited.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing an inter-metal dielectric layer. A substrate having a plurality of wires formed thereon is provided. A portion of the substrate is exposed to form an opening between the wires. The opening is filled with a flowable dielectric material, wherein a surface level of the flowable dielectric material is lower than that of the wires. A plurality of spacers is formed on the sidewalls of the wires exposed by the flowable dielectric material. The flowable dielectric material is removed. An anisotropic deposition process with a poor lateral-filling ability is performed to form a dielectric layer with a void under the spacer and over the substrate. Additionally, the method of manufacturing the inter-metal dielectric layer further comprises a step of forming a liner layer on the wires and the substrate before the step of filling the opening with the flowable dielectric material. Moreover, the flowable dielectric material is made of spin-on polymer or organic spin-on-glass. Furthermore, the anisotropic deposition process with a poor lateral-filling ability includes sputtering.
As embodied and broadly described herein, the invention provides a method of manufacturing an inter-metal dielectric layer with a relatively low dielectric constant. Because the inter-metal dielectric layer formed by the invention possesses a void under each spacer and the dielectric constant of the air in the void is about 1.0, the dielectric constant of the inter-metal dielectric layer is decreased. Incidentally, the dielectric constant of the inter-metal dielectric layer is varied with the size of the void and the size of the void can be adjusted to meet the requirement of the devices. The void can be adjusted by controlling the thickness of the flowable dielectric material and the width of the bottom of the spacers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5955786 (2000-09-01), Avanzino et al.
patent: 6013569 (2000-01-01), Lur et al.
patent: 6035530 (2000-03-01), Hong
Wolf, Stanley, “Silicon Processing For The VLSI Era”, vol. 2, Lattice Press, p. 168, 212-217, and 335,1990.
Nguyen Ha Tran
Niebling John F.
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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