Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...
Reexamination Certificate
1998-12-22
2001-01-09
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Radiation or energy treatment modifying properties of...
C432S005000, C432S006000, C432S200000
Reexamination Certificate
active
06171982
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and an apparatus for heat-treating an SOI substrate and also to a method of preparing an SOI substrate using the same. More particularly, the present invention relates to a method and an apparatus for heat-treating an SOI subsrate having a silicon film, and also to a method of preparing an SOI substrate using the same.
2. Related Background Art
In the technological field of silicon type semiconductor devices and integrated circuits, much research has been conducted to date on devices having a semiconductor on insulator (SOI) structure produced by utilizing a single crystal semiconductor film formed on a film insulator because such devices provide a reduced parasitic capacitance, an improved resistance against radiation and an easy device isolation; these features which can lead to a high speed/low voltage operation of transistors, a low power consumption rate, an enhanced degree of adaptability to integration and a significant reduction in the number of manufacturing steps including elimination of the well-producing steps.
Known substrates having an SOI structure (SOI substrates) include SOS (silicon on sapphire) substrates, those prepared by oxidizing the surface of an Si single crystal substrate, forming an window to expose part of the Si substrate and realizing a lateral epitaxial growth by using that area as seed to form a Si single crystal film (layer) on the SiO
2
surface, those prepared by using a Si single crystal substrate itself as an active layer and forming a silicon oxide film thereunder, those prepared by using a substrate having a dielectrically isolated Si single crystal region on a thick poly-crystalline Si layer and surrounded by a V-shaped groove and SOI substrates prepared by means of dielectric isolation involving oxidation of porous Si, which is referred to as FIPOS (full isolation by porous silicon).
Recently, SIMOX (separation by implanted oxygen) technology and wafer bonding technology have been in the main stream of SOI structure production technology. The SIMOX technology was reported for the first time in 1978 (K. Izumi, M. Doken and H. Ariyoshi, Electron. Lett. 14 (1978) p.593). It provides a method of forming a buried silicon oxide film by implanting oxygen ions into a silicon substrate and subsequently heat-treating it at high temperature.
The wafer bonding technology provides, on the other hand, a variety of techniques for thinning one of the bonded wafers in the process of producing an SOI structure.
BPSOI
This is one of the most basic processes that utilizes polishing. A silicon oxide film is formed on the surface of one or both of a pair of wafers, which are bonded together. Subsequently, one of the wafers is thinned by grinding and polishing.
PACE
The plasma assisted chemical etching (PACE) process was developed to improve the uniformity of film thickness of an SOI layer obtained by polishing. With this technique, the film thickness is measured at thousands of highly densely distributed measuring points on the wafer. Then, a plasma source having a diameter of several millimeters is driven to scan the film at a scanning rate corresponding to the film thickness to vary the etching rate as a function of the film thickness distribution and thereby reduce the variations in the film thickness.
Cleave Process using Hydrogen Ion Implantation
A novel technique for producing a bonded SOI substrate was recently reported by M. Bruel in Electronics Letters, 31 p. 1201 (1995) and also disclosed in Japanese Patent Application Laid-Open No. 5-211128 and U.S. Pat. No. 5,374,564. With this process, an oxidized wafer that has been implanted with ions of a light element such as hydrogen or an inert gas element over the entire surface thereof is bonded to another wafer and subsequently heat-treated. Then, the wafer is cleaved during the heat treatment at the depth to which ions have been implanted. As a result, the layer located above the projection range of implanted ions is transferred onto the other wafer to produce an SOI structure.
Epitaxial Layer Transfer
Japanese Patent No. 2608351 and U.S. Pat. No. 5,371,037 describe an excellent technique for preparing an SOI substrate by transferring a single crystal layer on a porous layer onto another substrate. This technique is also referred to as “ELTRAN (registered tradename)” (T. Yonehara, K. Sakakguchi, N. Sato, Appl. Phys. Lett., 64 p. 2108 (1994)).
As discussed above, in the field of SOI substrates, smoothing the rough surface produced as a result of etching, ion implantation and subsequent heat treatment and forming an SOI layer of silicon film with a low boron concentration by partly removing boron atoms diffused into the single crystal layer are the major problems that have to be solved to improve the withstand voltage of the gate oxide film and the carrier mobility of MOSFET in order to improve the performance of silicon type semiconductor devices. Thus, various techniques have been proposed to solve these problems for each of the above-listed methods for preparing SOI substrates.
With the cleave process using hydrogen ion implantation, the surface of the wafer separated along the ion projection range shows a root-mean-square of surface roughness (Rrms) of 10 nm, and the surface layer has damage caused by ion implantation. Such a wafer is smoothed to remove the layer damaged by ion implantation by polishing and removing the surface layer to a small extent using a technique referred to as “touch polishing” (M. Bruel, et al., Proc. 1995 IEEE Int. SOI Conf., p. 178 (1995)).
With the PACE technique, the surface roughness up to 10.66 nm (as peak-to-valley value) is detected by means of an atomic force microscope immediately after the plasma etching process. Such a rough surface is then smoothed to 0.62 nm, or to the level equivalent to the original surface roughness, by touch polishing for removing the surface only to a slight extent (T. Feng, M. Matloubian, G. J. Gardopee, and D. P. Mathur, Proc. 1994 IEEE Int. SOI Conf., p. 77 (1994)).
When the BESOI technique is used, the surface roughness of about 5 to 7 nm peak to valley produced at the end of the etching process is removed only by removing the surface layer by three to five times of the surface roughness or by 20 to 30 nm. As a result of this polishing process, the uniformity of film thickness is degraded by 0.005 &mgr;m (=5 nm) on average.
Thus, when touch polishing or kiss polishing, as it is often called, is used to polish the surface only to a slight extent, the surface roughness may be removed. However, at the same time, the film thickness will be reduced to consequently degrade the uniformity of film thickness. While the polishing operation is terminated generally by controlling the duration of the operation, it is a known fact that, if the polishing time is constant, the extent of polishing varies within the same surface of a wafer, among the surfaces of different wafers and from batch to batch depending on the polishing solution, the temperature of the surface table during the polishing operation and how much the emery cloth is worn. Hence it is very difficult to keep the extent of polishing to a constant level. Particularly, it is known that the wafer is normally polished more along the outer periphery.
Additionally, it is impossible to reduce the boron concentration if boron is diffused across the entire depth of the SOI layer to show a high concentration level. The surface roughness of the SOI layer of a wafer prepared by the SIMOX technique using oxygen ion implantation is greater than that of the bulk normally by a digit. S. Nakashima and K. Izumi (J. Mater. Res., vol. 5, no. 9, p. 1918 (1990)) reported that the surface roughness with innumerable recesses having a diameter of tens of several nanometers can be eliminated by heat-treating the surface at 1260° C. (in a nitrogen atmosphere) for 2 hours or at 1300° C. (in an argon atmosphere containing oxygen by 0.5%) for 4 hours. They also reported that the surface roughness will not change by heat
Bowers Charles
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Kielin Erik
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