Static information storage and retrieval – Read/write circuit
Reexamination Certificate
1999-08-26
2001-03-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
C365S149000
Reexamination Certificate
active
06201741
ABSTRACT:
DESCRIPTION OF THE RELATED ART
Conventionally well-known semiconductor memories to and from which data can be written and read at the same time include, e.g., a field memory (frame memory), a multiport memory, and a two-port memory incorporated in logic LSI (logic large scale integration).
FIG. 8
shows a configuration of an example a related field memory (frame memory).
A DRAM (dynamic random access memory) memory cell array
201
comprises memory cells (DRAM memory cells) requiring so-called refresh operations that are disposed in the row and column directions, each memory cell being located by a row address and a column address for locating the respective positions.
When data is written, data (serial input) to be written to a field memory, a row address corresponding to a memory cell to which to write the data, and a column address as a write address are supplied.
The row address is decoded supplied to an X decoder
203
and the decoded row address is supplied to a DRAM memory cell array
201
. This determines memory cells in the row direction to which to write the data.
The write address as a column address is decoded supplied to a serial decoder
207
. Furthermore, the data to be written is supplied to an SRAM (static random access memory)
208
or
209
. In the SRAM
208
or
209
, in accordance with the result of decoding the column address in the serial decoder
207
, the data to be written, to be supplied thereto, is temporarily stored. Thereafter, the data stored in the SRAM
208
or
209
is written supplied to a memory cell of the row determined by the result of decoding the row address in the X decoder
203
.
The SRAMs
208
and
209
are alternately used by performing bank switching. Specifically, after data to be written is stored in either of the SRAMs
208
and
209
, while the data is being written to the DRAM memory cell array
201
, the next data to be written is stored in the other. By this process, data is successively written.
On the other hand, when data is read, the row address of a memory cell in which data (serial output) to be read from the field memory is stored, and a read address as a column address is supplied.
The row address is decoded supplied to the X decoder
203
and the decoded row address is supplied to the DRAM memory cell array
201
. This determines memory cells in the row direction from which to read data. Data is read from the memory cells in the row direction and is amplified and latched in a sense amplifier
202
. The amplified and latched data is temporarily stored supplied to the SRAM
2051
or
2061
.
On the other hand, the read address as the column address is decoded supplied to a serial decoder
2041
. From the SRAM
2051
or
2061
in which the data read from memory cells of the row specified by the row address is stored, the data is read in accordance with the result of decoding the column address in the serial decoder
2041
and is output out of the field memory.
The SRAMs
2051
and
2061
are alternately used by performing bank switching, like the SRAMs
208
and
209
. specifically, after data read from memory cells is stored in either of the SRAMs
2051
and
2061
, while the data is being read out of the field memory, the next data read from memory cells is stored in the other. By this process, data is successively read.
In
FIG. 8
, the re are provided a serial decoder
2041
, and SRAMs
2051
and
2061
, and similarly configured serial decoder
2042
, and SRAMS
2052
and
2062
. Namely, two read ports are provided, thereby enabling simultaneous reading of two pieces of data.
In the above described field memory, by presenting a write address as a column address and a read address at the same time, data can be read and written at the same time.
When the timing of data transfer from the DRAM memory cell array
201
to the SRAM
2051
or
2061
(SRAM
2052
or
2062
) coincides with the timing of data transfer from the SRAM
208
or
209
to the DRAM memory cell array
202
, namely, when the timings of reading and writing data from and to the DRAM memory cell array
202
coincide with each other, either writing or reading is performed precedently by the arbiter not shown.
The size (capacity) of the SRAMs
2051
,
2052
,
2061
,
2062
,
208
, and
209
is determined based on the frequency of data (serial input) to be written and the operating speed of the DRAM memory cell array
201
to allow for the concurrent execution of data reading and data writing in the DRAM memory cell array
201
.
FIG. 9
shows a configuration of an example of a related multiport memory (dual port memory).
FIG. 9
uses identical reference numerals for corresponding portions in FIG.
8
.
Referring to
FIG. 9
, two ports, random I/O (input/output) and serial I/O, are provided, and row addresses or column addresses are decoded supplied to the X decoder
203
or Y decoder
211
.
When data is read or written via random I/O, the data is read from or written to a memory cell located by the result of decoding a row address or column address in the X decoder
203
or Y decoder
211
, respectively. When data is read or written via serial I/O, memory cells of a row located by the result of decoding a row address in an X decoder
204
are targeted for processing and data stored therein is read and supplied to the SRAM part
211
, or data stored in the SRAM part
211
is written.
A multiport memory as described above allows concurrent execution of data reading and data writing in a manner that writes data via either random I/O or serial I/O and reads data via the other.
In other words, for example, when data is written via random I/O and data is read via serial I/O, data to be written is input via the random I/O and a row address and a column address for locating a memory cell to which to write the data are input. As described above, a row address or a column address is decoded in the X decoder
203
or Y decoder
211
, respectively, and the data to be written is written to a memory cell of the DRAM memory cell array
201
located by the decoding result.
A row address for locating the row of a memory cell in which data to be read is stored is supplied at a timing slightly different from the timing at which a row address for locating the row of a memory cell to which to write data to be written is supplied, and the row address is also decoded in the X decoder
203
. The data is read from memory cells of a row located by the decoding result and is supplied to and stored in the SRAM part
211
.
On the other hand, a serial address for specifying an address of the SRAM part
211
is supplied to a Y decoder
212
for serial access, which decodes the serial address. Data is read from the address of the SRAM part
211
correspondingly to the decoding result and is output via serial I/O.
In
FIG. 9
, the SRAM part
211
comprises two SRAMs
2111
and
2112
, thereby enabling a continuous serial transfer of data by a split buffer transfer method. Specifically, after data supplied to the SRAM part
211
is stored in either of the SRAMs
2111
and
2112
, while the data is being transferred, the next data to be supplied to the SRAM part
211
is stored on the other of the SRAMs
2111
and
2112
. This enables continuous input/output of data.
Each of the SRAMs
2111
and
2112
has a storage capacity equivalent to the half of the number of columns of memory cells constituting the DRAM memory cell array
201
.
As described above, according to a storage device and a control method of the storage device of the present invention, the storage device comprises storage means having storage units specified by first and second addresses, specification means for specifying storage units of the storage means correspondingly to a first address, and a plurality of switching means, disposed in parallel, for making a storage unit corresponding to a second address capable of data reading and writing, of the storage units corresponding to the first address, wherein when a plurality of second addresses are specified, the switching means is controlled such that storage units correspon
Kondo Tetsujiro
Okumura Akihiro
Frommer William S.
Frommer Lawrence & Haug LLP.
Ho Hoai V.
Nelms David
Simon Darren M.
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