Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-02-03
2001-08-21
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S622000, C438S623000, C438S780000, C438S781000
Reexamination Certificate
active
06277766
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the fabrication of dielectric layers on semiconductor devices, and more specifically to methods for forming these from fullerene-decorated nanoparticles that will reduce the line capacitance of integrated circuits, and therefore improve their power consumption and delay time.
BACKGROUND OF THE INVENTION
Microelectronic integrated circuits based on patterned semiconductor materials are continuing to evolve towards devices with an extremely high density of circuit elements per unit volume. As the features of these devices are reduced to smaller sizes, the performance of the various materials that constitute the device will critically determine their success. One specific area in need of advancement is the electrical insulator used between the wires, metal lines, and other elements of the circuit. As the distances between the circuit elements become smaller, there will be increased problems due to capacitive coupling (crosstalk) and propagation delay. These difficulties can be avoided by preparing the circuit using an insulating material that possesses a dielectric constant as low as possible. It has been conventional prior art and practice in this field to use dense materials such as silicon dioxide, silicon nitride, and various organic polymers as insulators. However, the dielectric constants of these materials range from 3.0-7.0, which will not be adequate for future circuits. The success of future circuits will depend on the development of materials with dielectric constants of less that 2.0, and approaching the limiting value of an air gap (1.0). As there are as yet no fully dense materials with a dielectric constant less than 2.0 (2.1 for polytetrafluoroethylene), considerable effort has been focused towards the development of porous dielectric materials. These can be thought of as composite materials, with the value of their dielectric constants being intermediate between that of air and the solid phase.
U.S. Pat. No. 4,987,101, issued to Kaanta, et al. on Jan. 22, 1992 describes a process to prepare fully porous (air gap) structures by depositing a removable material in the critical area of the device, applying a solid cap to this material, and removing the temporary filler through holes bored in the cap. This requires several difficult process steps to completely eliminate all material from the desired areas. Additionally, there would be no mechanical support provided by the air gap. This could lead to deformations of the circuit as the device is cycled through high temperatures in subsequent processing steps.
U.S. Pat. No. 5,103,288 issued to Sakamoto and Hamano on Apr. 7, 1992 describes depositing an intimate mixture of metal oxides on a semiconductor wafer, one or more of which can be removed by chemical means. Extraction of the desired oxide components would leave a porous matrix of the remaining oxide. However, the available oxides that can be easily removed (sodium oxide, calcium oxide, etc.) contain cations that are generally considered to be impurities in semiconductor devices. Furthermore, there is a high probability that there will be incomplete removal of the desired oxide in this process that would adversely affect the dielectric performance of the material.
U.S. Pat. No. 5,494,859 issued to Kapoor on Feb. 27, 1996 describes a process whereby a composite material is deposited on a wafer by chemical vapor methods. This composite contains at least one component that can be removed by themochemical processing, thereby leaving the remaining portion of the composite as a porous layer. This process suffers from the rather expensive vacuum processing equipment needed for deposition of the composite and the high temperatures required to remove the unwanted portion.
A similar approach, taught by Rostoker and Pasch in U.S. Pat. No. 5,744,399 issued on Apr. 28, 1998 involves the formation of a thin layer of a matrix-forming material, filled with fullerene (C
60
, C
70
, etc.) molecules. These fullerenes are subsequently removed by chemical or physical means. Again, this procedure requires the removal of a considerable amount of material from the film to achieve a sufficiently high porosity. This can be very problematic in common integrated circuit processing.
The most common approach taken to achieve porous films on semiconductor wafers draws upon the methods of sol-gel chemistry. These methods typically employ the hydrolysis and condensation reaction of metal or metalloid alkoxides to form a gel containing a continues solid phase of the corresponding metal or metalloid oxide. This gel is filled with the solvent and other liquid reactants used in the process that must be removed to achieve a porous solid matrix. This well-developed process produces porous materials with fine particle sizes (2-10 nm) and very high porosities (70-99%). U.S. Pat. No. 4,652,467 issued to Brinker et al., on Mar. 24, 1987 describes preparing such a gel of silicon oxide. This gel is then dried by evaporative methods yielding a film of pure silicon dioxide. However, there is significant shrinkage resulting from the further condensation reaction of the silica particles as the gel structure is drawn together by the surface tension of the evaporating liquids. This leads to high-density films and increases their dielectric constant. A method to avoid the problem of gel shrinkage during drying has been developed by Gnade, et al, and Cho, et al. and described in U.S. Pat. No. 5,470,802, issued Nov. 28, 1995, and several subsequent patents. This process involves a further chemical derivitization of the silicon dioxide surface with an unreactive organic group. This prevents condensation reactions as the gel shrinks, and allows low-density materials to be prepared by evaporative drying. These sol-gel processes necessitate that several chemical reactions be performed after the alkoxide precursor solution has been applied to the wafer. This leads to difficulties of reproducibility and low throughput. Additionally, as the dielectric constant of porous silicon dioxide varies linearly with porosity (from 3.9 at full density, to 1.0 at full porosity) a very high porosity will be needed to achieve dielectric constants less than 2.0. This fact, and the random nature of the gelation process, increase the likelihood of encountering extremely large pores that would be detrimental to circuit fabrication.
Ayers, in U.S. Pat. No. 5,801,092 issued Sep. 1, 1998, teaches the formation of a dielectric layer prepared from SiO
2
, nanospheres coated with an organic layer. These spheres are then deposited on a substrate and crosslinked to form an integral film. However, the high temperatures encountered in integrated circuit processing necessitate the use of fluorocarbon materials as the organic component. Fluorine has been found to be highly corrosive to the fine-structured metal elements found in integrated circuits.
Therefore, to provide a low dielectric constant layer with low corrosivity, high thermal stability, and a known, controllable porosity, there is a significant need to develop new organic-inorganic hybrid materials. Additionally, there is a need for such a material that can be easily deposited on semiconductor wafers with standard wafer processing techniques.
An attractive class of molecules for use as the organic component in such a hybrid material is the fullerenes. These are pure carbon molecules with polycyclic cage structures of the formulae C
60
, C
70
, and higher molecular weight analogues. Their unique structure gives the fullerenes many attractive properties, most notably very high thermal stability. Furthermore, fullerenes can be easily combined with various inorganic substances to provide a desirable hybrid material.
SUMMARY OF THE INVENTION
The limitations of the prior art discussed above have, as of yet, not allowed the use of porous materials in semiconductor devices. Several of these limitations are overcome or alleviated by the present invention, which provides a route to the preparation of fullerene-decorated inorganic nanoparticles
Lytle Craig P.
Smith Matthew
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