Semiconductor memory device which activates column lines at...

Details Semiconductor memory device which activates column lines at... Semiconductor memory device which activates column lines at...

1999-09-24

2001-06-05

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189050, C365S189110

Reexamination Certificate

active

06243317

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device, such as a DRAM (dynamic random access memory), and more particularly to the activation of column select lines.
FIG. 17
schematically shows the configuration of an ordinary DRAM. The DRAM comprises memory cell arrays (MCA)
171
a
,
171
b
, row decoders (RDC)
171
c
,
171
d
, row segment selectors (RSS)
171
e
,
171
f
, column decoders (CDC)
171
g
,
171
h
,
171
i
, column segment selectors (CSS)
171
j
,
171
k
,
171
l
, a column address buffer (CAB)
171
m
to which a column address is inputted, a row address buffer (RAB)
171
n
to which a row address is inputted, a row command buffer (RCB)
171
o
to which a row-system command is inputted, a column command buffer (CCB)
171
p
to which a column-system command is inputted, and sense amplifier areas (S/A)
171
q
,
171
r
,
171
s
in which sense amplifiers are placed. On the memory cell arrays
171
a
,
171
b
, data line pairs DQ, /DQ (/ denotes an inverted signal) are provided. These data line pairs DQ, /DQ are connected to bit lines via column select gates, which will be explained later.
The memory cell arrays
171
a
,
171
b
include memory cells MC, word lines WL for selecting the memory cells, and bit lines BL. On both sides of each of the memory cell arrays
171
a
,
171
b
, the sense amplifier areas
171
q
,
171
r
,
171
s
are provided. When more than one row of memory cell arrays exists, a group of memory cell arrays set in the same row is called a row segment and a group of memory cell arrays set in the same column is called a column segment.
The row segment selectors
171
e
,
171
f
select a row segment according to a row address. The row decoders
171
c
,
171
d
select a word line in the memory cell arrays in the row segment selected by the row segment selectors
171
e
,
171
f
. The column segment selectors
171
j
,
171
k
,
171
l
select a column segment in the selected row segment according to a column address and the output signals of the row segment selectors
171
e
,
171
f
. The column decoders
171
g
,
171
h
,
171
i
select a column select line CSL in the column segment selected according to the column address and a row address. The selected column select line CSL drives a column select gate (not shown), thereby selecting a bit line BL.
When data is inputted to or outputted from the memory cell arrays
171
a
,
171
b
, the row command buffer
171
o
inputs a command to activate a word line and a row address is inputted to the row address buffer
171
n
. Part of the row address selects one or more of the row segments and the remaining row address selects one word line in the selected row segment.
For example, as shown in
FIG. 18
, the DRAM is assumed to have four memory cell arrays MCA
0
to MCA
3
. It is assumed that each memory cell has 512 word lines and two memory cell arrays are activated simultaneously. Eight CSL (column select lines) (not shown) are assumed to be on each sense amplifier area S/A. Row addresses R
0
to R
8
determine which word line in the row segment should be activated and row address R
9
determines which of the consecutive memory cell arrays should be activated. Because there are four memory cell arrays in the example, word lines in the two memory cell arrays MCA
0
and MCA
2
are activated as shown by solid lines. As a result, the data in the memory cells connected to the activated word lines are read by the sense amplifiers.
To access the data read by the sense amplifiers, a read command is supplied to the column command buffer
171
p
and a column address is supplied to the column address buffer
171
m
. The column address determines which sense amplifier should supply the data to the data line pair DQ, /DQ.
Recently, a logic-incorporated memory where a logic circuit has been incorporated into a memory core chip has been developed. Since in the logic-incorporated memory, a large amount of data is transferred between the memory section and logic section, a large I/O width (bit width) is needed. As a result, the number of data lines connected to the input/output terminals is also very large, leading to a large number of column select gates connected to a single column select line CSL. Such a memory often employs an overlaid DQ system in which the data lines are placed above each memory cell array.
FIG. 19
shows an example of the overlaid DQ system. In the overlaid DQ system, many column select gates CSG are connected to a single column select line CSL. As a result, the gate capacitance included in the column decoder and connected to a single driver DRV for driving the column select line becomes very great. The capacitance increases a delay in the transfer of the signal. Consequently, as the signal transmitting over the column select line goes further away from the driver DRV, its waveform becomes duller, which makes a high-speed operation more difficult.
To prevent this, the configuration of
FIG. 20
has been considered. In the configuration, blocks of the same construction composed of, for example, a column segment selector CSS, a column decoder CDC, and a driver DRV are placed on both sides of the memory cell arrays MCA. The column select line CSL is driven on both sides. In this case, however, blocks of the same construction have to be placed on both sides of the memory cell arrays. In the case of a complex logic column segment selector CSS, the size of its circuit is large. Consequently, the layout of the blocks requires very large areas, which causes the problem of making the layout size greater.
BRIEF SUMMARY OF THE INVENTION
It is, accordingly, an object of the present invention to overcome the above disadvantages by providing a semiconductor memory device capable of not only activating the column select lines reliably at high speed but also preventing the layout size from increasing.
The foregoing object is accomplished by providing a semiconductor memory device comprising: a memory cell array with memory cells arranged in the directions of row and column in matrix form; column select gates for selecting columns in the memory cell array; column select lines which are connected to the column select gages and transmit activating signals for activating column select gates; column decoders which are connected to one end of the column select lines and produce the activating signals according to an address; and driving circuits which are connected to the other end of the column select lines and which receive the activating signals supplied via the column select lines from the column decoders and drive the column select lines.
With the present invention, the column decoders are connected to one end of the column select lines and the driving circuits are connected to the other end of the column select lines. The column select lines are driven by the column decoders and driving circuits. This prevents the signal transmitted over the column select lines from becoming dull and therefore enables a high-speed operation. In addition, the driving circuits are simple in construction, which prevents the layout area from increasing.
Furthermore, the foregoing object is accomplished by providing a semiconductor memory device comprising: memory cell arrays with memory cells arranged in the directions of row and column in matrix form; column select gates which are provided near the memory cell arrays and select columns in the memory cell arrays; column select lines which are connected to the column select gates and transmit activating signals for activating column select gates; a select signal generator circuit which is provided on the side of one end of the column select lines and generates a select signal for selecting the memory cell array according to an address; a first decoder which is connected to one end of the column select lines and generates the activating signals according to an address and the select signal supplied from the select signal generator circuit; and a second decoder which is connected to the other end of the column select lines and, together with the first decoder, gen

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