Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-11-29
2001-08-07
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S158000, C438S151000, C438S149000
Reexamination Certificate
active
06271064
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor which is suitable for incorporation into a static random access memory (SRAM),
In general, thin film transistors may be used instead of load resistors in SRAMs having densities exceeding 1 megabit. Thin film transistors are also widely used as switching elements for switching image data signals in pixel regions of a liquid crystal display device.
Ideally, in either application, the off current of the thin film transistor should be low, while on current should be high in order to reduce power consumption and improve memory characteristics. That is, the thin film transistor should have a high on/off current ratios.
Much research has focused on achieving a thin film transistor with improved on/off current ratios.
A method for manufacturing a thin film transistor in an attempt to achieve an improved on/off current ratio is shown in
FIGS. 1
a
-
1
e.
In particular, these figures illustrate processing steps for manufacturing a conventional bottom gate thin film transistor on a semiconductor substrate.
As shown in
FIG. 1
a,
a first insulating film
2
is formed on a semiconductor substrate
1
. After depositing a polysilicon layer
3
on first insulating film
2
, polysilicon layer
2
is patterned by conventional photolithography and etching techniques according to a gate mask, thereby forming a gate electrode
3
a.
As shown in
FIG. 1
, through a chemical vapor deposition (CVD) method, a gate insulating film
4
and a polysilicon body layer
5
are successively deposited on the entire exposed surface of gate electrode
3
a
and first insulating film
2
. Then, during a 24 hour heat treatment growth step, the wafer is subjected to a temperature of approximately 600° C. As a result, the grain size of polysilicon layer
5
is enlarged.
As shown in
FIG. 1
c,
a photoresist film is next coated on body polysilicon layer
5
and patterned by conventional ensure and development processes to form a photoresist pattern PR
1
, which masks a channel region. At this time, with photoresist pattern PR
1
serving as can ion-implantation mask, impurity ions are implanted into the exposed body of polysilicon layer
5
, thereby forming source region
6
a
and drain region
6
b
(
FIG. 1
d
).
Accordingly, where the impurity ions are not implanted in polysilicon body layer
5
, a channel region A is formed, while another region between gate electrode
3
a
and drain region
6
b
serves as offset region B.
As shown in
FIG. 1
e,
after removing photoresist pattern PR
1
, a second insulating film
7
is formed on the entire surface of channel region A, off-set region B, source region
6
a
and drain region
6
b.
Second insulating film
7
is then patterned to form contact holes to sources region
6
a
and drain region
6
b,
respectively. Then, the contact holes are filled with a conductor to thereby form a source electrode
8
and a drain electrode
9
as wiring electrodes.
The operation principle of such conventional thin film transistor is as follows.
To begin with, if the transistor shown in
FIG. 1
e
is a P-type MOS thin film transistor, channel region A has n conductivity and source region
6
a
and drain region
6
b
have p conductivity. Accordingly, if a negative voltage is applied to gate electrode
3
a
relative to source region
6
a,
holes accumulate in channel region A, thereby forming a channel. If a negative voltage is applied to drain region
6
b
relative to source region
6
a,
a current flows between source region
6
a
and drain region
6
b,
due to the potential difference between the source and drain. However, if no voltage is applied to gate electrode
3
a,
a channel is not formed, and current is disrupted.
As shown in
FIGS. 1
a
to
1
e,
channel region A and offset region B are both defined using photoresist pattern PR
1
. However, if photoresist pattern PR
1
is misaligned, high off-current can result, thereby reducing reliability of the above-described thin-film transistor.
Further, while the conductivity of offset region B is adjusted in order to decrease the off-current, the conductivity of region B is not affected by the potential on gate electrode
3
a.
Thus, the series resistance is increased, causing drain current drivability to deteriorate.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, it is an object of the present invention to provide a thin film transistor and a method of manufacturing the same which has an off-set region of uniform length by using a self-alignment method, thereby improving a reliability of the thin film transistor.
It is another object of the present invention to provide a thin film transistor and a method of manufacturing the same, in which the potential of an off-set region is controlled by a gate electrode voltage, thereby improving on-current
According to one aspect of the present invention to accomplish the above objects, there is provided a thin film transistor comprising a substrate; a gate electrode formed on the substrate and divided into both edge parts and a mid part. An insulating film is formed on the surface of the gate electrode having a thickness on one of the edge parts of the gate electrode that is greater than that on the mid part and the other edge part. In addition, an active region is formed on the surface of the insulating film and the exposed substrate including an off-set region disposed so as to correspond to a channel region, a source region, a drain region and one edge part of the gate electrode.
According to another aspect of the present invention to accomplish the above objects, there is provided a method of manufacturing a thin film transistor, comprising the steps of: forming a conductive layer on a substrate and patterning the conductive layer to thereby form a gate electrode; defining the gate electrode as two edge parts and a mid part therebetween; forming a gate insulating layer on the surface of the gate electrode and the substrate and forming an insulating layer on the gate insulating layer; patterning the insulating layer to thereby remove only a portion on one edge part of the electrode; forming a semiconductor layer as an active region on the remained part of the insulating layer and the entire surface of the gate insulating layer; and implanting an impurity ion after masking a portion corresponding to the mid part and one edge part of the gate electrode, to there by form a source and a drain on opposite sides of the gate electrode, respectively.
According to another aspect of the present invention to accomplish the above objects, there is provided a method of manufacturing a thin film transistor, comprising the steps of: sequentially forming a conductive layer and a first insulating layer on the surface of a substrate; patterning the first insulating layer to thereby form a first insulating layer pattern having a predetermined width; forming a second insulating layer on the surface of the conductive layer and the first insulating layer pattern and etching the second insulating layer to thereby form sidewall spacers on both sidewalls of the first insulating layer pattern; etching the conductive layer using the first insulating layer pattern and the sidewall spacers as an etch mask, to thereby form a gate electrode; removing the sidewall spacers and growing side insulating films on both sides of the exposed gate electrode; removing one of the side insulating films and forming a third insulating layer on the surface of the gate electrode and the other side insulating film; forming an active region on the surface of the substrate and the third insulating layer; forming an impurity-containing layer on the active region and etching back the impurity-containing layer until the surface of the other side insulating film and the active region disposed between both sides insulating films are exposed; and diffusing the impurity from the impurity-containing layer to the active region by ann
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Lee Eddie
LG Semicon Co. Ltd.
Richards N. Drew
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