Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-07-24

2001-09-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S230080, C365S233100, C365S225700

Reexamination Certificate

active

06285606

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices, and more particularly to redundancy circuits for synchronous semiconductor memory devices.
BACKGROUND OF THE INVENTION
The storage capacity of semiconductor memory devices has continued to increase at a remarkable rate. The increase in storage capacity can be attributable to a number of factors, including but not limited to, advancements in processing technology and/or reductions in the size of various features within a semiconductor memory device. Reduced features sizes include smaller spacings between repeated structures (smaller “pitch”), as well as reductions in the size of particular components, such as conductive line widths, transistors, capacitors, and the like.
Due to the great number of memory cells and high complexity of most semiconductor memory devices, it can be very difficult to consistently manufacture devices that are completely free of defects. If all semiconductor devices having any sort of defect were completely discarded, the manufacturing yield of such devices would be significantly lowered. In order to increase fabrication yield, most semiconductor devices include some sort of redundancy scheme.
A redundancy circuit typically replaces one circuit element (such as a defective “ordinary” memory cell) with another (such as a redundant memory cell). In operation, when an address is applied to a memory device that corresponds to a defective ordinary memory cell, a redundancy circuit can detect such an address and prevent the defective ordinary memory cell from being accessed. Instead, the redundancy circuit can provide access to a redundant memory cell. In order to maintain operating speeds, it is desirable for an access to a redundant memory cell to be indistinguishable from an access to an ordinary memory cell and vice versa.
In this way, even if a semiconductor memory device includes defective memory cells (due to uncontrollable process variation, for example) it can still be fully functional through the use of redundancy circuits. This can allow semiconductor memory devices with defective memory cells to be packaged and provided as working devices. Consequently, the overall fabrication yield can be increased.
In many cases, even in the most advanced manufacturing processes, increases in semiconductor memory capacity may result in corresponding increases in defects. Thus, as semiconductor memory devices continue to increase in capacity, more and more redundant memory cells are included to account for possible defects. The resulting increases in redundancy circuits arising from larger numbers of memory cells may adversely affect access times to the semiconductor memory device.
To better understand the various features and advantages of the present invention, a conventional semiconductor memory device with redundancy circuits will now be described. A conventional semiconductor memory device is shown in
FIG. 21
, and may be a synchronous semiconductor memory. As shown in
FIG. 21
, a semiconductor device may include ordinary memory cell areas
001
, a redundant memory cell area
002
, Y decoder circuits
003
, a redundancy Y switching circuit
004
, Y predecoder circuits
005
, and a redundancy circuit section
006
.
Y decoder circuits
003
and redundancy switching circuit
004
may be situated in close proximity to cell areas
001
and
002
. Y predecoder circuits
005
and redundancy circuit section
006
may be situated in the periphery of cell areas (
001
and
002
), but likewise are in close proximity to such areas.
Y decoder and Y predecoder circuits (
003
and
005
) can be provided to access ordinary memory cells in ordinary memory cell areas
001
. As but one example, Y predecoder circuits
005
may receive address signals, and generate predecoded address signals. Such predecoded address signals may be received by Y decoder circuits
003
that may then select one or more ordinary memory cells.
Redundancy circuit section
006
and redundancy Y switching circuit
004
can be provided to access redundant memory cells in redundant memory cell area
002
. More particularly, redundancy circuit section and redundancy switching circuit (
006
and
004
) may receive address values and determine if an address value corresponds to a defective ordinary memory cell. If an address value does not correspond to a defective memory cell, an access can proceed as described above with respect to Y decoder and Y predecoder circuits (
003
and
005
). If an address corresponds to a defective ordinary memory cell, redundancy circuit section and redundancy switching circuit (
006
and
004
) can disable a Y predecoder circuit
005
and select one or more redundant memory cells from a redundant memory cell area
002
.
Referring now to
FIG. 22
, a diagram is set forth showing various signals that may be applied and generated in the conventional memory device of FIG.
21
. To that extent, like structures will be referred to by the same reference characters.
As shown in
FIG. 22
, an address signal YAjT may be received. In the particular example illustrated, within the term “YAjT” a value j may be a positive integer and the value T may indicate a logic high level.
Various signals are generated depending upon to whether or not the address signal YAjT corresponds to a defective ordinary memory cell.
If an address signal YAjT does not correspond to a defective ordinary memory cell, a redundancy circuit section
006
can receive the address and determine that it does not correspond to a defective memory cell. Consequently, decode enable signal YREDB can remain active and redundancy Y switching activation signals RYS can remain inactive. With decode enable signals YREDB active, Y predecoder circuits
005
can predecode address signal YAjT and provide predecoded address signal YPRD to Y decoder circuits
003
. According to predecoded address signals YPRD, Y decoder circuits
003
can access one or more ordinary memory cells (e.g., for a read or write operation) with Y select signals YSW. With redundancy switching activation signals RYS inactive, redundant memory cells in a redundant memory cell area
002
are not accessed.
If an address signal YAjT corresponds to a defective ordinary memory cell, a redundancy circuit section
006
can receive the address and determine such a correspondence. Consequently, decode enable signals YREDB can be deactivated and redundancy Y switching activation signals RYS can be activated. With decode enable signal YREDB inactive, Y predecoder circuits
005
can be disabled, and so do not generate predecoded address signal YPRD for Y decoder circuits
003
. Thus, an ordinary memory cell is not accessed in response to an address signal YAjT. Instead, with redundancy Y switching activation signals RYS active, a redundancy switch circuit
004
can access one or more redundant memory cells according to redundancy Y select signals RYSW. In this way, a defective ordinary memory cell may be replaced by a redundant memory cell.
The operation of a redundancy circuit section
006
may be timed according to a clock synchronization signal YRD. A clock synchronization signal YRD may be a synchronous with an externally applied clock signal.
Various signals described with reference to
FIG. 22
will now be described in more detail in FIG.
23
.
FIG. 23
is a representation of an integrated circuit “chip” that may include a conventional semiconductor memory device. As noted above, such a semiconductor memory device may be a synchronous device. In such a case, the synchronous semiconductor memory device may receive an external clock signal. Further, input signals may be received and output signals may be provided in synchronism with such an external clock signal.
In response to an external clock signal, a synchronous semiconductor memory device may generate an internal clock signal, shown as ICLK. An internal clock signal ICLK may be used to generate an address signal YAjT and a clock synchronization signal YRD. More particularly, a synchronous semiconductor memory device may inc

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