Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-27
2001-03-13
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S392000
Reexamination Certificate
active
06201274
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to the structure of a non-volatile semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
As to a conventional semiconductor memory device, various structures and manufacturing methods are proposed. Especially, as to a non-volatile semiconductor memory device as one of the conventional semiconductor memory devices, various techniques are proposed for problems such as the increase of operation speed and the realization of large capacity.
As an example of the proposals, in the flash memory with an erase gate described in U.S. Pat. No. 5,095,344, the high voltage of 20 V is used in case of an erasing operation. Also, it is reported in “A 2.3 &mgr;m
2
MEMORY CELL STRUCTURE FOR 16 Mb NAND EEPROMs” by R. SHIROTA et al. (IEEE, IEDM 1990) that the high voltage of 18 V in case of a writing operation and of 20 V in case of an erasing operation is used in the NAND type flash memory device. In this way, it is known as general knowledge in the flash memory art that the high voltage of about 20 V is used in the writing and rewriting operations for the high speed operation.
However, when the high voltage of about 20 V is used in the flash memory chip, it is necessary to provide the circuit for selectively applying the high voltage to memory cells of a memory circuit section. For this reason, the transistors which are used to drive and control such a memory circuit section are required to have the voltage endurance higher than the applied voltage.
It has been proposed to use a transistor which has the voltage endurance equal to or higher than 20 V. In this proposal, the source and drain diffusion layers are deeply formed such that the junction voltage endurance can be set to be equal to or higher than 20 V.
Such a well region forming method is proposed in “TWIN-TUB CMOS A TECHNOLOGY FOR VLSI CIRCUITS” by L. C. Parrillo et al. (IEEE, IEDM in 1980). In this method, a double well region structure and a threefold well region structure of P-type wells and N-type wells are formed. As shown in
FIG. 1
, when an N-type well region
303
and a P-type well region
302
are continuously formed on a substrate
301
, a step
304
is always formed between the different well regions
302
and
303
.
Also, as shown in
FIG. 2
, there is a case that a transistor is formed using a semiconductor substrate
401
having well regions such that a P-type well region
402
is used for a channel region, N-type well regions
403
and
404
are used for source and drain regions. A gate electrode
406
is arranged on the P-type well region
402
through an insulating film
405
. In this case, as shown in
FIG. 2
, steps
407
are formed between the source region and the channel region and between the drain region and the channel region. When a wiring layer is formed for the transistor in this state, projection portions are formed in the wiring layer due to the steps
407
. For this reason, there is a problem that electric field centers on the projection portions such that the wiring layer is broken or damaged. As a result, the reliability of the wiring layer is decreased. Also, when a high voltage transistor using well regions as the source and drain regions is formed in a flash memory device which has a large step between a memory cell region and a peripheral circuit region, the difference between the memory cell region and the peripheral circuit region becomes further larger due to the step.
As described above, in the conventional memory device, there is the problem that the steps are generated in the channel region so that the reliability of the high voltage transistor is decreased, when the well regions are used for the source and drain regions in the high voltage transistor. This is because the electric field centers on the steps so that the gate insulating film of the high voltage transistor is degraded.
Also, there is another problem that the difference between the memory cell region having a high substrate surface and the peripheral circuit region having a low substrate surface is increased. This is because the fine pattern forming process becomes difficult in the subsequent process because of the increased difference.
Further, there is still another problem that when the peripheral circuit region is formed apart from the memory cell region, another process of forming an insulating film and removing the insulating film is necessary, if a conventional impurity diffusion process is used in the manufacturing method.
In additional, an addition process for forming a reference mark is necessary so that the number of process steps is increased. As a result, the producibility decreases.
SUMMARY OF THE INVENTION
The present invention is accomplished in view of the above problems. Therefore, an object of the present invention is to provide a semiconductor device including a high voltage transistor and a method of manufacturing the same.
Another object of the present invention is to provide a semiconductor device including a non-volatile semiconductor memory device in which high integration is possible with high reliability, and a method of manufacturing the same.
In order to achieve an aspect of the present invention, a semiconductor device having a high voltage transistor, includes a first well region of the high voltage transistor formed in a semiconductor substrate as a channel region and having a first conductive type. Second well regions of the high voltage transistor are formed in the semiconductor substrate as a source region and a drain region to sandwich the first well region and have a second conductive type. A surface of the first region and surfaces of the second well regions have a flat plane.
The semiconductor device may further include a first transistor operating in a higher voltage than a second transistor and formed on the semiconductor substrate, in addition to the high voltage transistor. In this case, the first transistor may be formed on the semiconductor substrate to have, as a channel region, a third well region of the first conductive type.
Also, the semiconductor device may comprise a memory section including the first transistor and a peripheral section including the high voltage transistor. In this case, the semiconductor device is a non-volatile semiconductor memory device.
In order to achieve another aspect of the present invention, a semiconductor memory device includes a memory circuit section formed on a semiconductor substrate, and a peripheral circuit section formed on the semiconductor substrate, for driving and controlling the memory circuit section. A surface of a region where the memory circuit section is formed is lower in height than that of a region where the peripheral circuit section is formed.
The surface of the region where the peripheral circuit section is formed is desirably flat.
Also, the memory circuit section may include a plurality of non-volatile semiconductor memory cell transistors.
Further, the peripheral circuit section may include a plurality of high voltage transistors. In this case, each of the plurality of high voltage transistors desirably has as a channel region composed of a first well region of a first conductive type, and as source and drain regions, second well regions of a second conductive type. A well region of the semiconductor substrate where the memory circuit section is formed is of the first conductive type.
In addition, the surface of the region on which the memory circuit is formed may be used as a reference mark.
In order to achieve still another aspect of the present invention, a method of manufacturing a semiconductor device, includes the steps of:
forming a recess region for a memory cell region on a surface of a semiconductor substrate;
performing a first ion implantation of first impurity ions of a first conductive type to the semiconductor substrate to form a well region of the first conductive type;
forming a resist film on the semiconductor substrate;
pattern
Fenty Jesse A.
Lee Eddie C.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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