Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2000-06-23
2001-09-11
Bowers, Charles (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S758000, C257S623000, C438S401000
Reexamination Certificate
active
06288454
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to a semiconductor wafer, and more particularly to a semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same.
BACKGROUND OF THE INVENTION
The manufacture of semiconductor wafers to create semiconductor integrated circuit devices typically involves a sequence of processing steps which fabricate the multi-layer structure generally associated with the integrated circuit devices. Such processing steps may include (1) the deposition of metals, dielectrics, and semiconductor films, (2) the creation of masks by lithography techniques, (3) the doping of semiconductor layers by diffusion or implantation, (4) the polishing of outer layers (e.g. chemical-mechanical polishing), and (5) the etching of layers for selective or blanket material removal.
It should be appreciated that during wafer fabrication, a given layer, including the features defined therein, must be aligned with one or more previous layers. For example, the vias associated with a given interlayer dielectric must be aligned with the pads or similar feature defined in the metal layer positioned below the interlayer dielectric. Hence, a semiconductor wafer typically has a number of alignment marks defined therein such that the patterning tools associated with a lithographic stepper can be aligned to the wafer during a lithography process.
One alignment mark arrangement which is commonly utilized is a “zero-level” phase grating arrangement. In such an arrangement, two or more diffraction gratings are etched into the silicon substrate of the semiconductor wafer prior to any other patterning. In order to align the wafer prior to patterning, the alignment system associated with the stepper impinges light on the alignment mark and thereafter collects and processes the first order diffraction spots from each of the diffraction gratings defined in the substrate. In this manner, subsequent layers may be aligned with previously fabricated layers in order to facilitate proper wafer fabrication.
One advantage to use of a zero-level alignment mark is that all subsequent alignments are performed relative to the same alignment mark. However, use of a zero-level alignment mark has a number of drawbacks associated therewith. For example, it is often difficult to maintain the topography of the alignment mark during the entire wafer fabrication process. In particular, the fabrication of the various subsequent layers often obscure the alignment mark thereby rendering the alignment mark undetectable by the alignment system associated with the stepper. Hence, wafer fabrication processes which have heretofore been designed typically include a number of processing steps which are dedicated to the “clearing” of the zero-level alignment marks. For example, fabrication processes which have heretofore been designed typically include a number of patterning and etch processes which are dedicated to material removal from the area proximate to the zero-level alignment marks. Such additional fabrication steps undesirably increase costs associated with fabrication of the semiconductor wafer.
In order to overcome the drawbacks associated with use of the zero-level alignment mark, a number of layer-to-layer alignment mark schemes have heretofore been developed. As shown in prior art
FIGS. 4A-4E
, the circuit patterning fabrication steps may be utilized to create alignment marks which are used for the alignment of subsequent circuit layers thereby eliminating the need to “clear” the zero-level alignment marks after each fabrication step. In particular, as shown in prior art
FIG. 4A
, a semiconductor wafer
100
is shown after via patterning of a first interlayer dielectric, but before via etching. More specifically, the semiconductor wafer
100
includes a silicon substrate
110
which has a pre-metal dielectric layer
112
, a first metal layer
114
, an inter-layer dielectric layer
116
, and a patterned resist layer
118
fabricated thereon. Note that the resist layer
118
is patterned so as to create a number of vias in the interlayer dielectric layer
116
in order to electrically connect the first metal layer
114
to a subsequent metal layer. It should be appreciated that any patterning associated with fabrication of the layers shown in prior art
FIG. 4A
was aligned by use of a zero-level alignment mark (not shown) defined in the substrate
110
.
As shown in prior art
FIG. 4B
, the semiconductor wafer
100
is then etched or otherwise processed so as to remove the portions of the inter-layer dielectric layer
116
not covered by the resist
118
so as to create a number of trenches
120
which collectively define a grating
122
. Note that the resist layer
118
has been stripped from the semiconductor wafer
100
in prior art FIG.
4
B. It should be appreciated that the print, etch, and strip process utilized to fabricate the trenches
120
in the inter-layer dielectric layer
116
are also utilized to fabricate a number of vias in the inter-layer dielectric layer
116
in the active regions of the semiconductor wafer
100
which will be utilized to electrically couple active circuit devices of the various layers to one another.
A conductive interconnect layer
124
, such as tungsten, is then deposited on the semiconductor wafer
100
as shown in FIG.
4
C. The tungsten layer
124
creates conductive plugs in the via holes which function to provide a conductive path through the vias in order to electrically couple the metal layer
114
to a subsequent metal layer. The material associated with the tungsten layer
124
is also deposited in the trenches
120
so as to form a second layer of trenches
126
associated with the alignment grating
122
. Note that the step height of the trenches
122
is the same as the resultant step height of the trenches
126
.
As shown in prior art
FIG. 4D
, in order to create a flat, planar surface for subsequent processing steps, the semiconductor wafer
100
is then polished, such as by chemical-mechanical polishing (CMP), in order to remove residual tungsten material prior to deposition of a subsequent metal layer. Once the semiconductor wafer
100
has been polished, a second metal layer
128
is then deposited on the semiconductor wafer
100
. Note that deposition of the second metal layer
128
creates a third layer of trenches
130
associated with the alignment grating
122
. It should be appreciated that the alignment grating
122
may then be utilized to align the alignment tools of a lithographic stepper (not shown) to the semiconductor wafer
100
in order to pattern circuit features in the second metal layer
128
thereby eliminating the need to utilize the zero-level alignment mark defined in the substrate
110
for such alignment. Moreover, it should be further appreciated that during fabrication of the second metal layer
128
, a second inter-layer dielectric layer (not shown), a second interconnect layer (not shown), and a third metal layer, a similar alignment grating (not shown) may be fabricated at another location on the semiconductor wafer
100
in the same manner as the alignment grating
122
in order to facilitate alignment of subsequent layers.
However, the layer-to-layer alignment technique shown in prior art
FIGS. 4A-4E
has a number of drawbacks associated therewith. For example, the tungsten CMP process (see prior art
FIG. 4D
) creates an asymmetry in the alignment grating
122
that varies from location to location on the semiconductor wafer
100
. Such asymmetry creates an offset between the true and apparent center of the trenches associated with the grating that undesirably results in misalignment. Certain of such misalignment may be accounted for during lithographic patterning; however, certain of such misalignment is random in nature thereby potentially causing defects in the semiconductor wafer
100
which undesirably increases costs associated with wafer fabrication.
Thus, a continuing need exists for a fabrication technique which accurately and efficiently creates
Allman Derryl D. J.
Hainds Curtis C.
Jurgensen Charles W.
Lee Brian R.
Bowers Charles
Kebede Brook
LSI Logic Corporation
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