Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-05-25
2001-06-26
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S127000, C438S455000
Reexamination Certificate
active
06251702
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to chip-on-board encapsulation. More particularly, the present invention relates to an encapsulant molding technique used in chip-on-board encapsulation wherein an oxidizable metal layer is patterned on a carrier substrate and a top surface of the oxidizable metal layer is oxidized to facilitate removal of unwanted encapsulant material deposited during the molding operation.
2. State of the Art
In the fabrication of semiconductor devices, a common circuit integration technique involves attaching individual semiconductor components, such as semiconductor chips, to a surface of a carrier substrate, such as a printed circuit board (e.g. FR-4), ceramic substrate, BT substrate, cyanate ester substrate, or silicon substrate, by any known chip-on-board attachment technique. Such chip-on-board attachment techniques include, but are not limited to, flip-chip attachment, TAB attachment, and wire bond attachment. After attachment, the semiconductor components may be encapsulated with a viscous liquid or gel insulative material (e.g., silicones, polyimides, epoxies, plastics, and the like) (“encapsulant material”) with a transfer molding technique. This encapsulation (depending on its formulation) allows each semiconductor component to better withstand exposure to a wide variety of environmental conditions, such as moisture, ion impingements, heat, and abrasion.
An exemplary transfer molding technique for forming an encapsulant over a semiconductor component is illustrated in
FIGS. 11-16
. It should be understood that the figures presented in conjunction with this description are not meant to be actual views of any particular portion of an actual semiconductor component or molding device, but are merely idealized representations which are employed to more clearly and fully depict the process of the invention than would otherwise be possible.
FIG. 11
illustrates a pair of semiconductor components
202
attached to a carrier substrate
204
and in electrical communication with the carrier substrate
204
through a plurality of wire bonds
206
. As shown in
FIGS. 12 and 13
, a multi-cavity encapsulant mold
208
is placed over the carrier substrate
204
and semiconductor components
202
(shown in shadow line in the top plan view illustrated in FIG.
12
), such that cavities
210
(shown in shadow line in the top plan view illustrated in
FIG. 12
) of the multi-cavity encapsulant mold
208
are substantially centered over each semiconductor component
202
. The multi-cavity encapsulant mold
208
is pressed against the carrier substrate
204
to prevent the border or other portions of the carrier substrate
204
from being covered by encapsulant material to be subsequently injected.
The cavities
210
of the multi-cavity encapsulant mold
208
are usually connected by an interconnection array of channels
212
connected to a central reservoir
214
(see
FIG. 12
) from which an encapsulant material, such as a molten particle-filled polymer, is fed under pressure. Usually, the channels
212
have constricted regions called “gates”
216
adjacent each cavity
210
, as shown in FIG.
13
. The gate
216
controls the flow and injection velocity of the encapsulant material
218
into each cavity
210
and forms a break point abutting the cavity
210
to permit removal of the excess channel encapsulant
222
which solidifies in the channels
212
, as shown in FIG.
14
. After the encapsulation of the semiconductor component
202
is complete and the encapsulant solidified, the multi-cavity transfer mold
208
is removed, as shown in FIG.
15
. The excess channel encapsulant
222
at locations defined by channels
212
is then leveraged (shown in shadow lines in
FIG. 15
) from the surface of the carrier substrate
204
and broken free at an indentation
224
formed by the gate
216
(see FIGS.
13
and
14
), called “gate break”, as shown in FIG.
16
.
The adhesion of the solidified encapsulant material
218
to the carrier substrate
204
must be very strong such that the solidified encapsulant material
218
does not detach from carrier substrate
204
. However, this strong adhesion is disadvantageous when attempting to remove the excess channel encapsulant
222
from the carrier substrate
204
. If the adhesion between the excess channel encapsulant
222
and the carrier substrate
204
exceeds the cohesive strength of the material of the carrier substrate
204
itself, the carrier substrate
204
will delaminate or rupture when the excess channel encapsulant
222
is leveraged from the surface of the carrier substrate
204
.
Various methods have been devised to prevent the excess channel encapsulant from adhering to the carrier substrate. One such method is presented in U.S. Pat. No. 5,542,171 issued Aug. 6, 1996 to Juskey et al. (“the Juskey patent”) which relates to treating a predetermined portion of the surface of the carrier substrate over which the mold channels will reside to prevent the excess encapsulant material thereon from adhering to the carrier substrate. The Juskey patent teaches selectively contaminating the surface portion with an ink or a polymer. A drawback of the Juskey patent is that applying inks or polymers to the carrier substrate surface risks contamination of the area adjacent a semiconductor chip, which contamination may prevent the adhesion of the encapsulant material over the semiconductor chip to the carrier substrate, resulting in a compromised package.
Furthermore, the technique taught in the Juskey patent would not be applicable to FR-4 substrates (flame retardant epoxy glass laminate). FR-4 substrate require a cleaning step, such as plasma cleaning, just before encapsulation to remove unwanted organic compounds in order to obtain sufficiently strong adhesion between the encapsulant material and the FR-4 substrate. Unfortunately, the plasma cleaning would also remove the ink or polymer as taught in the Juskey patent and, as mentioned above, addition of inks or polymers after such cleaning would risk contamination of the area adjacent a semiconductor chip. Thus, for an FR-4 substrate, the predetermined surface portion on the carrier substrate is plated with gold. The gold plating adheres to the FR-4 substrate, but not to most encapsulant materials. Also, this non-adhering property of the gold to encapsulant materials is not affected during the plasma cleaning of the carrier substrate. However, such gold plating is expensive.
An alternative arrangement of channels which injects the encapsulant material from the top (i.e., no excess encapsulant material on the carrier substrate when encapsulating the semiconductor component) has been used, but this requires a more complex and expensive molding system.
Thus, it can be appreciated that it would be advantageous to develop an inexpensive technique to treat a predetermined portion of the surface of the carrier substrate, over which the transfer mold channels will reside to prevent the excess encapsulant material from sticking to the carrier substrate while using commercially-available, widely-practiced semiconductor device transfer-molding packaging techniques.
SUMMARY OF THE INVENTION
The present invention relates to an encapsulant molding technique used in chip-on-board encapsulation wherein an oxidizable metal layer is patterned on a carrier substrate and a top surface of the oxidizable metal layer is oxidized to facilitate removal of unwanted encapsulant material.
The oxidizable metal layer is applied, by any known means, over a specific portion of the carrier substrate to reside at a bottom of an interconnect channel of an encapsulant mold used in a subsequent transfer molding step. Oxidizable metals, such as copper, silver, or the like, adhere to carrier substrates, such as FR-4, ceramic, or silicon substrates. The oxidizable metal layer is then oxidized to form a metal oxide layer in and/or on an upper surface of the oxidizable metal layer. Such a metal oxide layer does not adhere to most encapsulant materials.
A semiconduct
Lattin Christopher
Micro)n Technology, Inc.
TraskBritt
Tsai Jey
LandOfFree
Use of an oxide surface to facilitate gate break on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Use of an oxide surface to facilitate gate break on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of an oxide surface to facilitate gate break on a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2459943