Semiconductor device with multiple contact sizes

Details Semiconductor device with multiple contact sizes Semiconductor device with multiple contact sizes

1999-07-15

2001-04-03

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S911000

Reexamination Certificate

active

06211058

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to semiconductor devices and methods for construction thereof. In particular, the invention relates to using different contact sizes at different layers of the semiconductor device in order to simplify and improve manufacturing techniques.
2. Related Art
In building semiconductor devices, such as NAND gates or other logic gates, it is necessary to make contact with various layers of the semiconductor device. This includes making contact with the first or second polysilicon layers or the silicon core.
FIG. 1
is an example of one such device. As shown in
FIG. 1
, a silicon core
101
has overlaid thereon a first polysilicon layer
103
which stores electrons. An oxide layer
102
can also be used between the silicon core
101
and the first polysilicon layer
103
. Polysilicon layer
103
is covered by a dielectric layer
105
. Dielectric Layer
105
is typically made up of an oxide layer
107
, a nitride layer
109
and another oxide layer
110
. Dielectric layer
105
has a second polysilicon layer
111
thereon. This layer often serves as the gate or word line where voltage is applied to turn on selected cells. The second polysilicon layer
111
also has thereon a tungsten silicide layer
113
. These layers are covered by an interlayer dielectric (ILD)
115
, which is polished to a uniform thickness. Metal interconnection lines
117
are then formed on top of the ILD
115
.
FIG. 1
also illustrates contact
119
contacting the core layer, contact
121
contacting the P1 layer, and contact
123
contacting the P2 layer. In conventional semiconductor devices, each of these contacts is the same size. Although each contact is the same size, it is necessary to etch different amounts of material to achieve the contacts at the different depths shown in FIG.
1
. For example, where the pattern is manufactured into each layer and the ILD material subsequently applied, the ILD must be etched away to a different depth for contacts
119
,
121
and
123
. Conventional systems attempt to achieve the uniform contact size by adjusting etch process parameters, such as chamber pressure, temperature or other parameters. This approach results in a complex manufacturing process, which is subject to error in etching to the correct depth.
SUMMARY AND OBJECTS OF THE INVENTION
It is an object of the invention to improve manufacturing techniques for semiconductor devices.
It is still another object of the invention to reduce the complexity of the etching process and to provide a simplified technique for manufacturing semiconductor devices, in particular, logic gates and further in particular, NAND gates.
It is a still further object of the invention to provide a semiconductor device with more accurately etched contacts.
It is a still further object of the invention to provide an improved process for forming contacts in semiconductor devices.
The above and other objects of the invention are accomplished in a semiconductor device which has a core region, a first polysilicon region or P1 region, and a second polysilicon region or P2 region. The semiconductor device according to the invention also has a plurality of contacts. Contacts to the P1 region are different in size from the contacts in the core region. According to another aspect of the invention, contacts in the P2 region are different in size from the contacts in the core region. In another aspect of the invention, contacts in the P1 and P2 regions are different in size from each other. In a further aspect of the invention, the size of the contacts in the P1, P2 and core regions are all different.
According to the invention, contacts to the P1 region are smaller than the contacts to the core region. In another aspect of the invention, contacts in the P2 region are smaller than contacts in the core region. In still another aspect of the invention, contacts in the P1 region are smaller than the contacts in the P2 region. According to another aspect of the invention, contacts in the P1 region are smaller than contacts in the P2 region which are smaller than contacts to the core region. One type device employing such a structure is a logic gate, and in particular, a NAND gate.


REFERENCES:
patent: 5177592 (1993-01-01), Takahashi et al.
patent: 5317193 (1994-05-01), Watanabe
patent: 5521409 (1996-05-01), Shieh et al.
patent: 5712509 (1998-01-01), Harada et al.
patent: 5760429 (1998-06-01), Yano et al.
patent: 5856706 (1999-01-01), Lee
patent: 59-76468 (1984-05-01), None
patent: 60-117771 (1985-06-01), None

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