Delay-locked loop with binary-coupled capacitor

Details Delay-locked loop with binary-coupled capacitor Delay-locked loop with binary-coupled capacitor

2000-05-12

2001-07-17

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C327S149000

Reexamination Certificate

active

06262921

ABSTRACT:

TECHNICAL FIELD
The present invention relates to integrated circuit devices, and more particularly, to delay-locked loop circuits in integrated circuit devices.
BACKGROUND OF THE INVENTION
Many high-speed integrated devices, such as a synchronous memory device
40
shown in
FIG. 1
, perform operations in a predetermined sequence. These operations are generally performed responsive to respective command signals issued by a command generator, such as a memory controller
44
.
It will be understood by one skilled in the art that the block diagram of
FIG. 1
omits some signals applied to the memory device
40
for purposes of brevity. Also, one skilled in the art will understand that the command signals COM may be composed of a combination of other signals or may be a packet of control data. In either case, the combination of signals or packet is commonly referred to as simply a command. The exact nature of these signals or packet will depend on the nature of the memory device
40
, but the principles explained above are applicable to many types of memory devices, including synchronous DRAMs and packetized DRAMs. Also, although the timing control by issuing command signals according to a fixed relationship with the clock signal will be explained with reference to memory devices, the principles described herein are applicable to other integrated circuits that utilize counters or related switching signals responsive to a clock signal.
Timing of operations within the device
40
is determined by a logic control circuit
42
controlled by an internal clock signal CKBUF. In a synchronous DRAM, the logic control circuit
42
may be realized conventionally. In a packetized memory system, the logic control circuit may include command sequencing and decoding circuitry.
Timing of signals outside of the memory device
40
is determined by an external clock signal CKIN that is produced by an external device
44
such as a memory controller. Usually, operations within the memory device
40
must be synchronized to operations outside of the memory device
40
. For example, commands and data are transferred into or out of the memory device
40
on command and data busses
48
,
49
, respectively, by clocking command and data latches
50
,
52
according to the internal clock signal CKBUF. Command timing on the command bus
48
and data timing on the data bus
49
are controlled by the external clock signal CKIN. To transfer commands and data to and from the busses
48
,
49
at the proper times relative to the external clock signal CKIN, the internal clock signal CKBUF must be synchronized to the external clock signal CKIN.
To ensure that the clock signals CKBUF, CKIN can be synchronized, the internal clock signal CKBUF is derived from the external clock signal CKIN. A buffer amplifier
46
buffers the external clock signal CKIN to produce a buffered version of the external clock signal CKIN as the internal clock signal CKBUF. The buffer amplifier
46
is a conventional differential amplifier that provides sufficient gain and appropriate level shifting so that the buffered clock signal CKBUF can drive circuits within the memory device
40
at CMOS levels.
The buffer amplifier
46
also induces some time delay so that the buffered clock signal CKBUF is phase-shifted relative the external clock signal CKIN. As long as the phase-shift is very minimal timing within the memory device
40
can be synchronized easily to the external timing.
Unfortunately, as the frequency of operation of the memory device
40
increases, the time delay induced by the buffer amplifier
46
may become significant. Consequently, commands or data supplied by the memory controller
44
may be gone from the command or data bus
48
,
49
before the latches
50
,
52
are activated on the appropriate edge of the buffered clock signal CKBUF. To prevent the latches
50
,
52
from missing commands that arrive synchronously with the external clock CKIN, the memory device
40
may be operated at lower frequencies. However, lower frequency operation of memory devices typically reduces the speed of operation undesirably.
To improve synchronization of the internal and external timing, a prior art memory device
60
shown in
FIG. 2
includes an analog delay-locked loop
62
that receives the buffered clock signal CKBUF and produces a synchronized clock signal CKSYNC that is synchronized to the external clock signal CKIN. To compensate for the delay of the buffer amplifier
46
, the synchronized clock signal CKSYNC is phase-shifted relative to the buffered clock signal CKBUF by an amount offsetting the delay of the buffer amplifier
46
. Because the synchronized clock signal CKSYNC is synchronized and substantially in phase with the external clock signal CKIN, commands and data arriving on the command bus
48
or data bus
49
can be synchronized to the external clock CKIN through the synchronous clock signal CKSYNC.
One problem with the memory device
60
of
FIG. 2
is that conventional delay-locked loops
62
typically operate only over a narrow frequency band. Consequently, the memory device
60
may not operate properly in multifrequency environments or in a wide range of applications.
Moreover, many conventional analog delay-locked loops include relatively sophisticated analog components that are not always easily integrated with digital memory components. Also, as operating conditions vary, the delay of the buffer amplifier
46
can vary, thereby causing corresponding variations in the phase shift. If the delay-locked loop
62
does not adjust the phase shift of the synchronous clock signal CKSYNC accordingly, operations within the device
40
may not remain properly synchronized to the external clock CKIN.
SUMMARY OF THE INVENTION
A delay-locked loop produces a plurality of phase shifted signals in response to an input signal at a selected input frequency. The delay-locked loop includes a variable delay circuit that outputs a delayed clock signal. A race detection circuit receives the delayed clock signal and the input clock signal and, depending upon whether the delayed clock signal leads or lags the input clock signal, the race detection circuit outputs an increment or decrement signal to a counter. In response to the increment or decrement signal, the counter increments or decrements a digital count signal.
The variable delay circuit includes a bank of selectable capacitors, each selectively coupled between a reference potential and a supply potential by a respective selection switch. Each of the selection switches is controlled by 1 bit of the digital count signal from the counter. If the corresponding bit is a “1,” the selection switch couples the capacitor in parallel with the other capacitors. The capacitance of the bank is determined by the number and capacitance of the selected capacitors. Because the delay of the delay circuit corresponds to the capacitance, the delay of the delay circuit is controlled by the digital count signal.
Each capacitor in the bank has a capacitance corresponding to the significance of its respective bit of the digital count. For example, the capacitor controlled by the most significant bit of the digital signal is the largest capacitor and the capacitor controlled by the least significant bit of the digital signal is the smallest capacitor.
In one embodiment, the race detection circuit is formed from a pair of pulse generators, each having its output coupled to a respective gating circuit. The gating circuits each include control ports and are responsive to control signals at the control ports to pass or block the pulse from the respective pulse circuit. The outputs of the gating circuits drive respective latch circuits. Each of the latch circuits includes an output coupled to control port of the gating circuit coupled to the other latch circuit so that the latches output the control signals. Thus, if a pulse passes through the first gating circuits and sets its corresponding latch, the latch output disables the second gating circuit and prevents the second latch from being set.
If both

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