Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-01
2001-03-20
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S361000, C257S362000
Reexamination Certificate
active
06204537
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electrostatic discharge (ESD) protection scheme for integrated circuit devices and, more particularly to an ESD protection scheme with improved turn-on performance.
As is explained in detail by S. Wolf in Silicon Processing for the VLSI Era, Volume 2, 1990, the input signals to a metal-oxide-silicon integrated circuit (MOS IC) are fed to the gates of MOS transistors within the integrated circuit. If the voltage applied to the gate insulator is excessive, the gate oxide will break down. The dielectric breakdown strength of SiO2 is approximately 8×10
6
V/cm; thus, most gate oxides will not tolerate voltages greater than 12-15 V without breaking down. Although this is well in excess of the normal operating voltages of 5 V integrated circuits, voltages higher than this may be impressed upon the circuit integrated circuit pads as a result of human-operator or mechanical handling operations.
The main source of such high voltages is triboelectricity (electricity caused when two materials are rubbed together). A person can develop very high static voltage (a few hundred to a few thousand volts) simply by walking across a room or by removing an integrated circuit from its plastic package. If such a high voltage is accidently applied to the pins of an IC package, the resulting electrostatic discharge (ESD) can cause breakdown of the respective gate oxides to which it is applied. The breakdown event may cause sufficient damage to produce immediate destruction of the device, or it may weaken the oxide enough that it will fail early in the operating life of the device.
It has become a widely held practice to provide ESD protection circuits for all the integrated circuit pads or pins of MOS ICs. The need for such circuits is particularly acute for VLSI devices in such high-noise environments as personal computers, automobiles, and manufacturing control systems. These protective circuits, normally placed between the input and output pads on a chip and the transistor gates to which the pads are connected, are designed to begin conducting or to undergo breakdown when the integrated circuit pads are at a relatively high electrical potential, thereby providing an electrical path to ground or the power supply rail. Since the breakdown mechanism is designed to be nondestructive, the circuits provide a normally open path that closes only when a high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected.
Unfortunately, many of the existing ESD protection schemes do not provide a sufficiently low threshold turn-on voltage for the associated integrated circuit or are prohibitively complex and expensive to manufacture. Accordingly, there is a continuing need for ESD protection schemes that provide a sufficiently low threshold turn on voltage while doing so with a semiconductor structure that is reliable and relatively inexpensive to manufacture.
BRIEF SUMMARY OF THE INVENTION
This need is met by the present invention wherein a reliable and low threshold ESD protection scheme is provided by modifying the structure of a conventional MOSFET device.
In accordance with one embodiment of the present invention, an integrated circuit device is provided comprising an integrated circuit pad, an internal integrated circuit, and an ESD protection circuit. The internal integrated circuit is conductively coupled to the integrated circuit pad so as to define a primary electrical path from the integrated circuit pad to the internal integrated circuit. The ESD protection circuit is conductively coupled to the integrated circuit pad so as to define a secondary electrical path from the integrated circuit pad to the ESD protection circuit. The ESD protection circuit comprises a semiconductor structure arranged to define a doped silicon substrate, a drain region, a source region, an electrically insulating region, and a gate structure. The drain region is formed in the silicon substrate and is conductively coupled to the integrated circuit pad via the secondary electrical path. The source region is formed in the silicon substrate and is conductively coupled to a relatively low electrical potential. The electrically insulating region is formed in the silicon substrate between the drain region and the source region. The gate structure is conductively coupled to a relatively low electrical potential and is arranged to define an incipient inversion layer in the drain region upon application of a relatively high electrical potential to the integrated circuit pad. The gate structure and the electrically insulating region are arranged to define an active gate region limited to extend from the drain region to the electrically insulating region.
The size and location of the electrically insulating region formed in the silicon substrate are preferably such that, upon application of the relatively high electrical potential to the integrated circuit pad, an electrostatic discharge current path between the source region and the drain region tends to follow a path through the silicon substrate substantially offset from the active gate region and around the electrically insulating region.
The doped silicon substrate preferably comprises a doped p-type silicon substrate and the drain region and the source region comprise doped n
+
regions. The relatively high electrical potential may be a positive electrical potential or a negative electrical potential.
In accordance with another embodiment of the present invention, an integrated circuit device is provided comprising an integrated circuit pad, an internal integrated circuit, and an ESD protection circuit. The ESD protection circuit comprises a semiconductor structure arranged to define a doped silicon substrate, a drain region, a source region, an electrically insulating region, and a gate structure. The gate structure of the ESD protection circuit is arranged to overlap a portion of the drain region such that, upon application of a relatively high electrical potential to the integrated circuit pad, gate-induced drain leakage current flows in the silicon substrate. Further, the gate structure and the electrically insulating region are arranged to define an active gate region limited to extend from the drain region to the electrically insulating region, such that the gate-induced drain leakage current tends to follow a path through the silicon substrate substantially offset from the active gate region.
The gate structure may further be arranged to define an incipient inversion layer in the drain region upon application of a relatively high electrical potential to the integrated circuit pad. The drain region, the source region, and the silicon substrate may be arranged to form a junction transistor having a characteristic breakdown voltage above which breakdown voltage breakdown current flows in the silicon substrate between the source region and the drain region. The gate-induced drain leakage current preferably reduces the characteristic breakdown voltage of the junction transistor and the size and location of the electrically insulating region formed in the silicon substrate are such that the resulting breakdown current tends to follow a path substantially offset from the active gate region.
In accordance with yet another embodiment of the present invention, an integrated circuit device is provided comprising an integrated circuit pad, an internal integrated circuit, and an ESD protection circuit. The ESD protection circuit comprises a semiconductor structure arranged to define a doped silicon substrate, a drain region, a source region, an electrically insulating region, and a gate structure. The electrically insulating region is formed in the silicon substrate between the drain region and the source region. The drain region and the source region extend a first predetermined distance into the silicon substrate from the upper surface of the silicon substrate and the electrically insulating region extends a second predetermined distance into the silicon substra
Eckert II George C.
Killworth, Gottman Hagan & Schaeff, L.L.P.
Lee Eddie C.
Micro)n Technology, Inc.
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