Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-30
2001-06-05
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S317000, C257S319000
Reexamination Certificate
active
06242773
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to semiconductor devices and, more particularly, to a non-volatile memory device having sub-micron features.
2. Background of the Art
The escalating requirements for high density performance associated with ultra large scale integration semiconductor devices requires design features of 0.25 microns and under (e.g., 0.18 microns and under), increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for competitiveness. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor manufacturing techniques. Moreover, as design features are reduced into the deep sub-micron range, it becomes increasingly difficult to maintain or improve manufacturing throughput for competitiveness.
Memory devices are one class of examples of semiconductor devices that require high density performance and ultra large scale integration. Memory cells can take a variety of forms, some being both electrically erasable and electrically programmable (Electrically Erasable Programmable Read Only Memory, or EEPROMs), and others requiring special exposure techniques, such as ultraviolet light, for erasing (Erasable Programmable Read Only Memory, or EPROMs). Memory cells such as EEPROMs and EPROMs are often referred to as non-volatile memory devices because they are capable of storing and retaining a charge that corresponds to a specific value, even after to the circuit has been shut off. One of the most critical components for charge retention in non-volatile memory devices such as EPROMs is the interpoly dielectric. This dielectric functions to insulate the floating gate (a first polysilicon layer) from the control gate (which is typically formed as a second polysilicon layer) so that a charge may be stored in the floating gate. Accordingly, charge loss is a major consideration in fabricating semiconductor devices, such as memory cells, that must successfully retain a charge.
A flash or block erase EEPROM (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line, and erased together as a block. An example of a memory cell of this type includes individual metal oxide semiconductor (MOS) memory cells. Each such MOS memory cells includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
FIG. 2A
illustrates an exemplary memory cell
200
. As shown, the memory cell
200
is viewed in a cross-section through the bit line. The memory cell
200
includes a doped substrate
210
having a top surface
211
, within which a source
212
a
and a drain
212
b
have been formed by selectively doping regions of a substrate
210
. A tunnel oxide
215
separates a floating gate
216
from the substrate
210
. An interpoly dielectric
224
separates the floating gate
216
from a control gate
226
. The floating gate
216
and the control gate
226
are each electrically conductive and typically formed of polycrystalline silicon. A silicide layer
228
is disposed on top of the control gate
226
, and functions to increase the electrical conductivity of the control gate
226
. The silicide layer
228
is typically composed of a tungsten silicide (e.g., WSi
2
) that is formed on top of the control gate
226
prior to patterning, using conventional deposition and annealing processes.
The memory cell
200
can be programmed, for example, by applying an appropriate programming voltage to the control gate
226
. Similarly, the memory cell
200
can be erased, for example, by applying an appropriate erasure voltage to a source
212
a
. When programmed, the floating gate
216
will have a charge corresponding to either a binary 1 or 0. By way of example, the floating gate
216
can be programmed to a binary 1 by applying a programming voltage to the control gate
226
, which causes an electrical charge to build up on the floating gate
216
. If the floating gate
216
does not contain a threshold level of electrical charge, then the floating gate
216
represents a binary 0. During erasure, the charge is removed from the floating gate
216
by way of the erasure voltage applied to the source
212
a.
FIG. 2B
illustrates a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A—A, as referenced in FIG.
2
A).
FIG. 2B
reveals that individual memory cells are separated by isolation regions of silicon dioxide formed on the substrate
210
. For example,
FIG. 2B
shows a portion of a first floating gate
216
a
associated with a first memory cell, a second floating gate
216
b
associated with a second memory cell, and a third floating gate
216
c
associated with a third memory cell. The first floating gate
216
a
is physically separated and electrically isolated from the second floating gate
216
b
by a first field oxide
214
a
. The second floating gate
216
b
is separated from the third floating gate
216
c
by a second field oxide
214
b
. The floating gates
216
a
,
216
b
,
216
c
are typically formed by selectively patterning a single conformal layer of polysilicon that has been previously deposited over the exposed portions of the substrate
210
, tunnel oxide
215
, and field oxides
214
a-b
. The interpoly dielectric layer
224
is conformably deposited over the exposed portions of the floating gates
216
a-c
and the field oxides
214
a-b.
The interpoly dielectric layer
224
isolates the floating gates
216
a-c
from the next conformal layer, which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form the control gate
226
. The interpoly dielectric layer
224
typically includes a plurality of films such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of memory cells, and in particular the features depicted in the memory cells of
FIGS. 2A and 2B
, places a burden on the fabrication process to deposit/form the floating gate
216
and control gate
226
without creating deleterious effects within the memory cell. Of particular concern, is the need to provide adequate isolation between each of the floating gates
216
a-c
, and between the floating gates
216
a-c
and the control gate
226
, while also providing an adequately arranged floating/control gate configuration.
As previously stated, a key factor in charge retention is the effectiveness of insulating the floating gate. Difficulty has been encountered in increasing manufacturing throughput and cost effectiveness of memory cells, because the manufacturing steps are complex and expensive. Furthermore, it is difficult to efficiently process multiple layers of devices such as memory cells without creating deleterious effects.
Conventional methodology for fabricating floating gates is illustrated in
FIGS. 3A-3C
, wherein similar reference numerals denote similar features. Referring to
FIG. 3A
, there is shown a floating gate structure during an early stage of fabrication. As shown in
FIG. 3A
, a semiconductor substrate
310
contains isolation regions
312
, such as field oxide regions. A tunnel dielectric or tunnel oxide
314
is formed on the surface of the semiconductor substrate
310
at a location between field oxides
312
. A layer of polycrystalline silicon
316
(polysilicon) is deposited on the entire semiconductor substrate
310
, including field oxides
312
and tunnel oxide
314
. Next, polysilicon layer
316
, and tunne
Advanced Micro Devices , Inc.
Chaudhuri Olik
Rao Shrinivas H
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