Smart debug interface circuit

Details Smart debug interface circuit Smart debug interface circuit

1998-06-10

2001-03-13

Le, Dieu-Minh T. (Department: 2785)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C712S227000

Reexamination Certificate

active

06202172

ABSTRACT:

TECHNICAL FIELD
The field of the present invention pertains to diagnostic testing and debugging of integrated circuit devices. More particularly, the present invention relates to a optimized diagnostic testing and debugging interface circuit for debugging programmable digital processor applications.
BACKGROUND ART
Many devices common to every day life utilize complex integrated circuits. Examples include desktop computer systems, video games, vending machines, and even pay phones. These devices often include programmable digital processors embedded within their systems. The digital processors typically implement any required user interface (e.g., a menu of choices) and execute the actual electronic processing required to implement user requests (e.g., place a phone call or order a service). The more complicated and sophisticated the device, the more complex the system including the programmable digital processor.
As these devices and their applications have become more sophisticated, the task of designing, testing, and debugging the digital systems implementing these devices his become much more difficult. The ever increasing sophistication dictates ever more densely populated integrated circuit boards and more highly integrated components. Validation of the system design and verification of proper functionality of the devices has become a major concern in developing new device applications.
In response to this concern, the electronics industry, under the auspices of the Institute of Electrical and Electronics Engineers (IEEE) has implemented a widely used and widely supported industry standard for the building of electronic devices. This standard, IEEE 1149.1-1990, was developed and promulgated by an industry Joint Test Action Group (JTAG). The “JTAG specification” requires that both system level and board level electronic devices include test access ports (TAPs) which allow access to internal circuit nodes and registers which are otherwise virtually inaccessible. The JTAG standard further describes a “boundary scan” architecture, an internal “serial scan” architecture, and a state machine which allows access to the state of internal signals and busses and the context of internal registers.
To implement the JTAG boundary scan architecture, the component or circuit board of a device needs to include boundary scan cells which are implemented between each component pin or circuit board connector. The boundary scan cells are connected together to form a scan chain (e.g., a shift register path) around the periphery of the integrated circuit, hence giving rise to the term “boundary scan”.
To implement the JTAG serial scan architecture, the component or circuit board of a device needs to include scan cells directly within the circuitry comprising the integrated circuit or component. While boundary scan cells are confined to the periphery, serial scan cells are located within the circuitry of the individual components or circuit boards. Serial scan cells can provide access to internal signals and internal registers which are inaccessible using boundary scan cells. The individual serial scan cells are connected serially to form a serial scan chain through the interior of the integrated circuit.
Both serial scan chains and boundary scan chains couple to a JTAG TAP (test access port). The TAP implements a JTAG compliant state machine which provides a standardized method of accessing the boundary scan architecture and/or serial scan architecture. The TAP is, in turn, coupled to a computer system which runs a testing and debugging program.
With reference now to prior art
FIG. 1
, a system
100
incorporating a boundary scan chain is shown. System
100
includes a programmable digital processor (e.g., digital signal processor
101
) having a eight data bus lines
103
a
-
110
a
. Each of the data bus lines
103
a
-
110
a
couple to a corresponding boundary scan cell
121
-
128
and subsequently couple to a memory controller
102
via bus lines
103
b
-
110
b
. As described above, each of boundary scan cells
121
-
128
couple serially to a TAP
130
via line
115
. The boundary scan cells
121
-
128
can function as latches, latching the value present on bus lines
103
a
-
110
a
as dictated by a debugging program via TAP
130
. The boundary scan cells
121
-
128
can also function as drivers, meaning they can drive values onto bus lines
103
b
-
110
b
. For example, when system
100
functions normally, signals present on bus lines
103
a
-
110
a
are “passed through” to bus lines
103
b
-
110
b
via boundary scan cells
121
-
128
. However, when system
100
functions in debug mode, boundary scan cells
121
-
128
can either read the values on bus lines
103
a
-
110
a
as they are passed through, or can drive test values onto bus lines
103
b
-
110
b
comprising test instructions for digital signal processor
101
.
There is a problem, however, in the fact that the test circuitry included in a device is not “transparent” to the circuitry comprising the device. For example, in system
100
, the circuitry comprising TAP
130
and boundary scan cells
121
-
128
have a number of adverse impacts on the performance of digital signal processor
101
. By inserting scan cells
121
-
128
between the digital signal processor
101
and the memory controller
102
, the bus between the digital signal processor
101
and the memory controller
102
is “broken” into two resulting busses comprised of bus lines
103
a
-
110
a
and
103
b
-
110
b
. By breaking the bus in this manner, a boundary scan delay is added to each word transmitted from digital signal processor
101
to memory controller
102
, as the word is passed through boundary scan cells
121
-
128
. The more demanding the application system
100
implements, the more problematic the boundary scan delay becomes.
There is a problem with serial scan chain architectures also. Although serial scan cells might avoid inducing boundary scan delays, the incorporation of serial scan cells into the circuitry of integrated circuit devices tends to be very expensive. To incorporate serial scan cells into an integrated circuit, the circuitry comprising the integrated circuit needs to be redesigned to include the circuitry comprising the serial scan cells. For example, for digital signal processor
101
to incorporate a serial scan chain, the circuitry comprising the serial scan chain is design into the circuitry comprising digital signal processor
101
. This increases the transistor count of digital signal processor
101
, the area of silicon required to fabricate digital signal processor
101
, and the complexity of digital signal processor
101
.
To avoid the above problems associated with serial scan chains and boundary scan chains, many system designers are incorporating specialized test monitoring code in the applications running on system
100
. The test monitoring code records the information via software as opposed to hardware. The test monitoring software, however, increases the size of the memory required for storing the “normal” application software. For some applications (e.g., a pay phone) this can be very problematic.
Thus, what is required is a solution which does not have the disadvantages of the prior art. The required solution should provide the benefits of conventional test interfaces while avoiding the adverse impacts on the programmable digital processor system under test. The required solution should be fully compatible with the industry standard JTAG interface. The required solution should not increase the size of the programmable digital processor integrated circuit by including numerous serial scan cells. The required solution should not impose a boundary scan delay by breaking the busses coupled to the programmable digital processor with boundary scan cells. Additionally, the required solution should not increase the amount of memory required to store the application software of the programmable digital processor system. The present invention satisfies the above requirements.
DISCLOSURE OF THE INVENTION
The present invention co

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