Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-01-06
2001-01-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S620000, C438S626000, C438S631000, C438S637000, C438S698000, C438S712000
Reexamination Certificate
active
06177337
ABSTRACT:
BACKGROUND OF THE INVENTION
In integrated circuit (IC) chips, patterns of metal are used to electrically interconnect the electronic components making up the integrated circuit. Proper interconnection of the various electronic components is essential to proper and reliable performance. Thus, the occurrence of short or open circuits or other defects in the interconnect structure(s) is problematic for overall reliability. Interconnect problems may be caused not only by defects in the interconnect structures themselves, but also by defects in the portions of the chip in the vicinity of the interconnect structure. Such defects may manifest themselves during subsequent manufacturing steps leading to chip rejection or during actual use leading to problems for the end user of the IC-containing device.
Typically, interconnects are formed by depositing a layer of the desired electrically conductive material (typically, a metal or alloy) on a semiconductor substrate (i.e. over whatever other layers may already present on the substrate). Auxiliary conductive layers (e.g. Ti or TiN) may be deposited before and/or after deposition of the electrically conductive metal layer such that the auxiliary layers lie directly above and/or below the electrically conductive metal layer. The auxiliary layers are generally used to enhance the device reliability and to act as barrier layers between interconnect metallurgy and other portions of the overall IC structure (e.g., underlying or overlying dielectric layers, etc.). Portions of the conductive material layer(s) (including any auxiliary layers present) are then removed selectively whereby the conductive material remaining on the substrate forms a pattern corresponding to the desired interconnect structure.
Formation of the desired interconnect structure from the deposited conductive layer(s) is usually achieved by applying a photoresist layer over the unpatterned conductive layer(s) (i.e. over the uppermost conductive layer). The photoresist is then pattern-wise exposed to radiation and developed (i.e. portions of the photoresist layer are removed) to reveal a photoresist pattern corresponding to the pattern of the desired interconnect structure. The conductive layer(s) is then typically etched to remove the portions of the conductive layer not covered by the photoresist pattern. When the desired removal is completed, the remaining photoresist is removed to reveal the conductive material pattern (i.e. the desired interconnect structure) on the substrate. Typically, the conductive material pattern (e.g. one or more lines) has vertical or sloped sidewalls such that the pattern at the underlying substrate surface is equal or greater ir area than the pattern at the top surface of the conductive material furthest from the underlying substrate surface.
Once the desired interconnect structure is formed, typically a dielectric layer is deposited over and between the features of the interconnect structure to protect and appropriately isolate the interconnect structure.
While the above process is generally known, defects (such as voids in the interconnect metallurgy or in the dielectric deposited adjacent to the interconnect structure) can be generated by the process. Defects can be tolerated to some extent, but defects become less tolerable with reduced feature dimensions and more complex designs associated with integrated circuit manufacture. Thus, there is a need for improved interconnect structure formation processes which reduce or eliminate the occurrence of defects.
SUMMARY OF THE INVENTION
The invention provides new techniques for forming electrically conductive interconnect patterns or other metal structures which reduce or eliminate the occurrence of defects in or near those structures. The invention also provides improved etching processes for etching metal-containing patterns and is especially applicable to the etching of metal-containing interconnect patterns. The methods of tt invention are especially useful for producing patterned metal structures having reentrant profiles resulting in structures having reduced stress levels.
In one aspect, the invention encompasses a method for forming a metal-containing structure over a dielectric structure on a semiconductor substrate, where the method comprises:
(a) providing a semiconductor substrate having a dielectric layer, a lower electrically conductive barrier layer, an electrically conductive metal layer, an upper electrically conductive barrier layer, and a patterned mask layer, wherein the lower barrier layer overlies the dielectric layer, the electrically conductive metal layer overlies the lower barrier layer, the upper barrier layer overlies the electrically conductive metal layer and the photoresist layer overlies the upper barrier layer such that portions of the upper barrier layer are exposed,
(b) treating the substrate as follows:
(i) contacting the exposed portions of the upper barrier layer under reactive ion etching conditions with a first gas mixture at a first pressure whereby a portion of the upper barrier layer is etched to expose portions of the electrically conductive metal layer,
(ii) contacting the exposed portions of the electrically conductive metal layer under reactive ion etching conditions with a second gas mixture at a second pressure whereby bulk of the electrically conductive metal layer thickness is anisotropically etched while avoiding exposure of the lower barrier layer, the second gas mixture having a different composition from the first gas mixture,
(iii) contacting the remaining exposed portions of the electrically conductive metal layer under reactive ion etching conditions with a third gas mixture at a third pressure whereby the remaining exposed portions of the electrically conductive metal layer is anisotropically etched to expose portions of the lower barrier layer, the third gas mixture having a different composition from the first and second gas mixtures, and
(iv) contacting the exposed portions of the lower barrier layer under reactive ion etching conditions with a fourth gas mixture at a fourth pressure to reveal portions of the underlying dielectric layer, the fourth gas mixture having a different composition from the second and third gas mixtures, and
(c) removing the mask layer to reveal the metal-containing structure which structure includes the remaining portions of the electrically conductive metal layer and the barrier layers.
Preferably the second pressure is less than the first pressure, the third pressure is greater than the second pressure, and the fourth pressure is less than the third pressure.
In another aspect, the invention encompasses metal interconnect structures and methods of making metal interconnect structures having isolated and/or nested line features wherein at least one of the line features has a reentrant profile. The invention is especially applicable for metal interconnect structures formed from aluminum, copper and/or alloys thereof.
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Berry Renee′ R.
Capella Steven
International Business Machines - Corporation
Nelms David
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