Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-04-02
2001-05-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06230304
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuit design and more specifically to a method for routing the interconnections between components on an integrated circuit.
BACKGROUND OF THE INVENTION
A cell-based integrated circuit is formed by selecting a plurality of cells that represent components having different characteristics from one or more cell libraries, determining interconnects for the selected cells, and then placing and routing the interconnected selected cells to form the integrated circuit. For example, groups of cells may be interconnected to function as flip-flops, shift registers and the like. This process, overall, is conventionally described in terms of logic description, synthesis of that logic, and then placement and routing of the synthesized logic.
Electrical connections of individual components on integrated circuits are achieved using conducting paths (also called “wires” or “nets”) between terminals of components which are to be connected. Automatic routing schemes are used to determine these conducting paths.
For more complex designs, there are typically at least four distinct layers of conducting medium available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing. It is a common practice to route each conducting path (“wire” or “net”) by using one or more of the distinct layers of conducting medium, with one layer of a pair being reserved predominantly for connections running along the “x” direction and the other layer for connections running in the orthogonal or “y” direction. Some of the layers, such as the metal layers, are exclusively used for interconnection of components. The polysilicon layer may have a dual role, such as forming the gates of transistors as well as for interconnection of components.
An electrical connection between two nets on adjacent layers is implemented with a “via” which is an etched or drilled hole in the substrate for allowing a conductive path to extend from one layer to another layer.
Conventional design methodologies typically use a two-step process for determining the final size and location of each net. The first step is the global routing step for roughly determining wiring routes. The “rough” wiring pattern generated in this step is known as a “global route.” Subsequently, a second detailed routing step for precisely determining a final routing pattern according to the global routes is used. This final routing pattern determined by the detailed routing step is known as a “detailed route.”
In one conventional design methodology, die size is fixed and imaginary grid lines are used to partition the die into a matrix of blocks. Thus, the grid lines are used by the automated place and route equipment to assist in determining and then tracking of the location of the various nets and components that make up the integrated circuit.
With conventional “fixed die” design methodologies, complete routing of all nets cannot be ensured. Although complete routing can be ensured using channel routing techniques, channel routing techniques impose additional constraints and have their own problems.
Co-pending related U.S. Patent Application entitled “Timing Closure Methodology,” which is fully incorporated herein by reference, describes a timing driven methodology, which methodology makes timing, but not area, a constraint. Accordingly, once placement of cells is determined based upon timing that has been fixed, the need exists to more efficiently route wires. Conventional routing techniques, including those mentioned above, can be used to route wires and connect cells whose placement has been determined by use of the timing driven methodology described above. However, conventional routing methodologies cannot efficiently ensure that the timing constraints are maintained. Accordingly, there is a need for a new routing method that works with the timing driven design methodology to provide more efficient and better results.
SUMMARY OF THE INVENTION
The invention broadly provides an automated method for designing an integrated circuit layout with a computer, based upon an electronic circuit description and upon a selected plurality of cells from a cell library, comprising the steps of:
(a) assigning each of the cells to one of a plurality of buckets designated on the integrated circuit layout, each of the cells being connected to one of the other cells;
(b) performing global routing to connect at least some of the selected cells of step (a) together such that global routes are formed to provide net topology information;
(c) performing track routing which sets the position of each of the global routes;
(d) performing detailed placement such that the positions of all selected cells are fixed within each of the buckets designated on the integrated circuit layout; and
(e) performing detailed routing such that detailed routes are formed to complete the integrated circuit layout.
The invention further provides an automated method for designing an integrated circuit layout with a computer, based upon an electronic circuit description and by using a cell library containing a selected plurality of cells, comprising the steps of:
(a) based upon a portion of a computer program that contains a sequence of instructions, assigning each of the cells to one of a plurality of buckets designated on the integrated circuit layout, each of the cells being connected to one of the other cells based upon the electronic circuit description input to the computer;
(b) performing global routing to connect at least some of the selected cells of step (a) together such that global routes are formed to provide net topology information;
(c) performing track routing which sets the position of each of the global routes;
(d) performing detailed placement such that the positions of all selected cells are fixed within each of the buckets designated on the integrated circuit layout; and
(e) performing detailed routing such that detailed routes are formed to complete the integrated circuit layout.
A automated method for designing an integrated circuit layout by using a computer and based upon an electronic circuit description, comprising the steps of:
(a) using a portion of a computer program that contains a sequence of instructions, placing a first plurality of cells in designated initial positions;
(b) forming a plurality of global routes based upon the designated initial positions of the first plurality of cells of step (a);
(c) fixing the positions of the global routes of step (b);
(d) placing a second plurality of cells based upon the positions of the global routes of step (c); and
(e) placing a plurality of detailed routes to complete the integrated circuit layout.
The present invention makes possible an advantage of providing a methodology for setting and achieving timing constraints for an-integrated circuit.
The invention also makes possible an advantage of providing a method to efficiently place cells and route wires based on fixed timing constraints for the desired circuit.
The invention further places timing driven routing at selected stages in the design process so as to optimize routing and placement results. The placement and routing results are further optimized since detailed placement is adapted based on the fixed positions of the.global routes.
The invention makes possible another advantage of enabling a faster process at later stages of the design process.
The invention makes possible an additional advantage of permitting capacitance control on a net-per-net basis which can lead to reduced die sizes.
Still another advantage made possible by the invention is the achievement of routing completion for an integrated circuit layout under constraints (e.g., timing constraints).
The invention also make possible an advantage of enabling detailed placement to be re-performed so as to achieve routing completion for the desired circuit.
The list of possible advantages and be
Groeneveld Patrick R.
van Ginneken Lukas P. P. P.
Do Thuan
Magma Design Automation Inc.
Pillsbury & Winthrop LLP
Smith Matthew
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