Method of fabricating interconnects

Details Method of fabricating interconnects Method of fabricating interconnects

2000-03-20

2001-08-07

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S624000, C438S637000, C438S688000, C438S700000, C438S780000, C438S782000

Reexamination Certificate

active

06271116

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89100466, filed Jan. 13, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a multilevel interconnect process, and particularly relates to a method of fabricating a metal interconnect process used for avoiding poisoned vias.
2. Description of the Related Art
In integration circuit process for semiconductor devices, the interconnects are provided between two devices to allow electrical connection. The present metal interconnect comprises multilevel metal layer to connect the devices in the circuit, since the density of integrated circuits has increased and the function has become more complicated.
The inter-metal dielectric layer (IMD) is used for isolating an upper metal layer and a lower metal layer. The upper and lower metal layers are connected by vias.
In the conventional multilevel interconnect process, an inter-metal dielectric layer is formed to cover a substrate having metal lines thereon. Thereafter, via openings are formed in the inter-metal dielectric layer by photolithography and etching, and then the via openings are filled with a metal plug layer to form vias. Other metal deposition processes, photolithography and etching are performed.
Organic polymer material that has a dielectric constant lower than the dielectric constant of silicon oxide is used as the inter-metal dielectric layer in deep sub-micron processes, in order to increase the device performance and reduce the resistance-capacitance time delay effect.
However, the organic polymer material that has a low dielectric constant is damaged while the photoresist is being removed by oxygen plasma. In the above method of fabricating the metal interconnects, after the via openings are formed by etching the inter-metal dielectric layer composed of the organic polymer material, the organic polymer material exposed by the sidewall of the via openings is damaged.
SUMMARY OF THE INVENTION
The present invention is a method of fabricating interconnects. A semiconductor substrate having metal lines is provided. A liner layer is formed over the substrate, and then a dielectric layer is formed between the metal lines, wherein the dielectric layer has a low dielectric constant (k). Patterned thermal conductivity layers are formed surrounding the predetermined regions of vias. Thereafter, another dielectric layer with low dielectric constant is formed between the patterned thermal conductivity layers, and then a planar cap layer is formed over the substrate. Via openings exposing the metal lines are formed in the planar cap layer, the patterned thermal conductivity layer and the liner layer. The via openings are filled with a metal material to form vias.
In one preferred embodiment of the method of the present invention, an inter-metal dielectric layer comprises four layers, which includes the liner layer, the dielectric layer, the thermal conductivity layer and the cap layer. The material of the dielectric layers is an organic material with low dielectric constant, the material of the thermal conductivity layer is an inorganic material with low dielectric constant and high thermal conductivity.
Since the inter-metal dielectric layer is formed by a great number of low dielectric constant materials, the resistance-capacitance time delay effect is reduced and the performance of the device is improved.
The vias and the low dielectric constant organic dielectric layers are surrounded with the thermal conductivity layer, the cap layer formed with silicon oxide and the liner layer formed with silicon oxide. The organic dielectric layers with low dielectric constant are not exposed by the via openings. The inter-metal dielectric layer on the sidewalls of the via openings is not damaged while removing a photoresist layer used for defining the via openings by oxygen plasma. The issue a poisoned via is avoided while filling the via openings with metal material.
The thermal conductivity layer is patterned to form dummy lines which are located surrounding the predetermined regions of the vias. The thermal conductivity layer has high thermal conductivity, so that the heat produced by the metal lines under high speed operation can be diffused. Therefore, the present invention can avoid the reliability problem arising from using the organic dielectric material.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5476817 (1995-12-01), Numata
patent: 5675187 (1997-10-01), Numata et al.
patent: 5858869 (1999-01-01), Chen et al.
patent: 6165893 (2000-12-01), Chung
patent: 6326431 (1994-11-01), None
patent: 101999882 (1998-07-01), None

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