Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-18
2001-08-21
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S306000, C257S208000
Reexamination Certificate
active
06278148
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device in which a plurality of functional blocks formed of a plurality of transistors are integrated on the same semiconductor chip. More particularly, the present invention relates to a semiconductor device in which functional blocks such as dynamic memories, analog circuits which are susceptible to noises, and digital logic circuits are integrated on the same semiconductor chip.
BACKGROUND OF THE INVENTION
Recently, with an advance in the degree of integration of large-scale integrated circuits (LSIs), it has been possible to integrate a large-scale logical circuit formed of large capacity memories and digital circuits, operation circuits, and analog circuits on a 1 cm×1 cm semiconductor chip, for example. In the near future, it is expected that so-called system-on-silicon, in which the whole system is integrated using such a chip, will be realized.
Japanese Patent Laid-Open No. 212185 (1996) discloses an example in which a large capacity memory and a CPU (Central Processing Unit), which is a large scale logic circuit, are integrated on the same chip. In this example, the memory is provided on the edge portion of the chip while logic circuits such as a CPU, peripheral circuits and interface circuits are arranged on the central portion of the chip. When the memory is provided only at the edge portion of a chip, as described in the prior art, there is the problem that the degree of freedom of a chip layout is lowered. Particularly, in an ASIC (Application Specific Integrated Circuit) realizing a function desired by users using a memory core, a CPU core, and the like, the decrease in the degree of freedom of the chip layout leads to an increased chip area.
The present inventor has studied the chip layout shown in
FIG. 2
, in which a dynamic memory and logical circuits are integrated. The semiconductor chip CHIP comprises logical blocks BLK
1
and BLK
2
each formed of digital circuits, and a dynamic memory DM disposed between the logical blocks BLK
1
and BLK
2
, and other elements. The logical block BLK
1
includes a logical circuit LC
1
while the logical block BLK
2
includes a logical circuit LC
2
. The blocks are connected to each other with the wiring WR
1
. Other wiring connections besides WR
1
are omitted for simplification.
Logical blocks BLK
1
and BLK
2
are arranged on both sides of the dynamic memory DM. Hence, when an output terminal of the logic circuit LC
1
is connected to an input terminal of the logic circuit LC
2
, its shortest route crosses over the dynamic memory DM. However, upon taking into consideration the influence on signals on WR
1
caused by noises generated from the dynamic memory DM as well as the change in potential influenced upon the dynamic memory DM due to wiring WR
1
, the wiring must be detoured around the dynamic memory DM to ensure stable operation. However, with a large number of wiring lines connecting the logical block BLK
1
with the logical block BLK
2
, such a detouring procedure causes an increase in wiring area, thus increasing the chip area. Moreover the problem arises that the wiring length becomes long so that the wiring delay makes it difficult to operate at high speed.
Of course, if only the wiring WR
1
is preferentially considered, the length of the wiring WR
1
can be shortened by closely arranging the blocks BLK
1
and BLK
2
. However, since there are many wiring layers between logical blocks and a dynamic memory and many wiring layers between logical blocks and bonding pads, in addition to the wiring WR
1
between blocks, the layout of functional blocks cannot generally be determined only by considering a specific wiring. As a result, memories or analog circuits must be arranged between a plurality of logic blocks or between logic blocks and bonding pads to be connected to each other with wirings.
Japanese Patent Laid-Open No. 121349 (1990) discloses that a cell using a circuit, internally including a node, which performs a dynamic operation is covered with a grounded wiring layer while a wiring between cells is formed over the grounded wiring layer. Moreover, Japanese Patent Laid-open No. 152968 (1991) discloses that a metal layer connected to the ground potential is formed between the wiring layer within a cell and the wiring layer between cells. However, these references do not teach the integration of dynamic memories and logical circuit blocks on a single semiconductor substrate. Moreover, the references do not teach the passing of wiring provided between logical blocks over the upper portion of the dynamic memory nor the necessity of doing so. In the prior art, the metal wiring layer, where a shielding metal is provided, is used only for shielding. The references do not teach that the metal wiring layer is used to pass signal wirings for a logical circuit.
SUMMARY OF THE INVENTION
Generally speaking, in an LSI integrating large-scale logic circuits and operation circuits, each having a large capacity memory and digital circuits, and analog circuits such as analog-to-digital converters and digital-to-analog converters, many wirings are needed for connections between functional blocks or between functional blocks and bonding pads. Hence, there is a problem in that the area occupied by the wirings results in an increased chip area and wiring delay. Furthermore, another important problem is that electrical noise generated from the signal lines affect the operation of analog circuits and digital circuits, which are susceptible to noises. Also, noises generated from a memory may induce noises in signal lines.
The first object of the present invention is to provide a memory-logic hybrid chip in which a dynamic memory and logical circuit blocks are integrated on a semiconductor substrate, so as to prevent the wirings and the chip area from being increased and to avoid the above-mentioned problems regarding noises and wiring delay.
The second object of the present invention is to provide a semiconductor device that can prevent the wirings and the chip area from being increased in such a manner that electrical noises induced in signal lines do not adversely affect the operation of a noise susceptible circuit portion.
A summary of typical aspects of the invention disclosed in the present application will be briefly described below.
In order to achieve the first object, according to the present invention, among logical blocks and dynamic memories integrated on the same semiconductor chip, upper portions of the dynamic memories are shielded with a conductive layer biased to the same equipotential. Wirings are passed over the conductive layer between the logical block and bonding pads or between a logical block and another logical block.
The dynamic memory generates coupling noises because a number of data lines are simultaneously charged when a sense amplifier amplifies a read-out signal. Immediately before the sense amplifier amplifies a read-out signal, the data line comes to an electrically floating state, so that the dynamic memory is susceptible to external noises. Generally speaking, the logical circuit requires more wiring layers than the memory circuit. In such a memory-logic hybrid chip, the memory section does not require a large number of wiring layers in comparison with the logic section. Hence, a feature of the present invention is that a shielding conductor is formed above the memory section which is susceptible to noise and wiring for a logic section can be performed in the same layer as that of the shielding conductor. This means that a memory-logic hybrid chip that can solve problems of noises and the increased chip area can be provided.
According to a more preferred mode of the present invention, the shielding conductor is also connected to the plate electrode of a memory cell capacitor. Since the shielding conductor is connected to the ground potential and acts as a power supply line to the plate of the memory cell capacitor, the configuration can be simplified.
Moreover, according to the present invention, to achieve the second object
Fukuda Takuya
Hasegawa Norio
Watanabe Takao
Cao Phat X.
Chaudhuri Olik
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
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