Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
1999-12-17
2001-05-08
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S185180, C365S189060, C365S194000, C327S390000, C327S589000
Reexamination Certificate
active
06229740
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to voltage generation circuits having a boost function. More specifically, the present invention provides a configuration of a voltage generation circuit capable of preventing excessive boosting of an output voltage even if the circuit is used at wide-ranging power supply voltage levels and suppressing a standby current in a period other than a boosting operation period, and a configuration of a semiconductor memory device provided therewith.
2. Description of the Background Art
With active development of devices requiring lower power consumption such as portable devices, semiconductor products have operated at lower voltage.
In a semiconductor memory device performing electrical data reading, erasing, writing and the like such as a flash memory, electrical storage data stored in a memory cell is generally read to a data line such as a bit line by applying an “H” level voltage to a word line. In order to achieve both lower voltage operation and higher speed data reading operation, it is essential that the “H” level voltage applied when a word line is to be driven is a voltage obtained by boosting a power supply voltage.
A circuit for generating the boosted voltage is called a word line boost circuit and provided in a semiconductor memory device. It is necessary to design the word line boost circuit so as not to uselessly consume power by operating the circuit only during a period in which generation of a boosted voltage is necessary and inactivating the circuit during other periods such as a standby period.
Semiconductor products have various power supply voltage levels according to their specifications. For example, the current flash memory market has roughly three types of power supply voltage ranges, that is, the versions of Vcc=1.6V~2.2V and Vcc=2.2V~2.7V which are regarded as lower power supply voltage versions, and the currently major version of Vcc=2.7V~3.6V.
In order to accommodate such various types of power supply voltage ranges, it is necessary to adjust boost capability according to a power supply voltage level in a word line boost circuit provided in a memory. Considering the case of the above described flash memory, it is necessary to switch boost capability according to power supply voltage range so that the boost capability is set to be larger for the Vcc=1.6V~2.2V version, smaller for the Vcc=2.2V~2.7V version, and boosting is not carried out for the Vcc=2.7V~3.6V version.
Such a method is adopted for switching the boost capability that the capacitance value of a boost capacitor provided in a word line boost circuit is separately provided by changing a mask pattern in a semiconductor device manufacturing process.
When the boost capability is switched by mask pattern changes, however, it is disadvantageously required that different masks are prepared and undergone separate manufacturing processes according to the power supply voltage range of a flash memory.
Otherwise, a power supply voltage level is detected and the capacitance value of a boost capacitor is made variable according to the power supply voltage level as a method of switching the boost capability according to the value of a power supply voltage.
FIG. 8
is a circuit diagram showing a configuration of a conventional voltage generation circuit
300
used as a word line boost circuit for generating a boosted voltage according to a power supply voltage level by adopting the above described method.
Referring to
FIG. 8
, voltage generation circuit
300
is a circuit for setting the voltage level Vbst of a voltage supply node
340
at one of a power supply voltage Vcc and a boosted voltage obtained by boosting Vcc. A boost control signal BST is activated to the “H” level when boosting is necessary and inactivated to the “L” level when boosting is not necessary.
Voltage generation circuit
300
includes a Vcc level detection circuit
305
receiving power supply voltage Vcc and setting a Vcc level signal LVL at the “H” level or the “L” level according to comparison between Vcc and a prescribed voltage, a boost circuit
310
transmitting one of power supply voltage Vcc and the boosted voltage to an output transistor
330
according to boost control signal BST and control signal LVL, a gate boost circuit
320
boosting the gate voltage of output transistor
330
according to boost control signal BST, and an output transistor
330
receiving an output of gate boost circuit
320
at its gate and provided to connect boost circuit
310
and voltage supply node
340
.
Boost circuit
310
includes a delay circuit
312
receiving boost control signal BST, applying delay time td to boost control signal BST, and outputting delayed boosted control signal BST, a boost capacitance switch circuit
314
switching the capacitance value of a capacitor, which is used for boosting, according to the delayed boost control signal and Vcc level signal LVL, and a voltage switch circuit
315
transmitting one of power supply voltage Vcc and the boosted voltage as an output of boost capacitance switch circuit
314
to output transistor
330
according to delayed boost control signal BST.
Boost capacitance switch circuit
314
has P type MOS transistors Q
21
, Q
22
and an N type MOS transistor Q
23
connected in series between a power supply line
342
and a ground line
344
. The gates of transistors Q
21
and Q
23
are supplied with delayed and inverted boost control signal BST which is an output of an inverter IV
11
. The gate of transistor Q
22
is supplied with Vcc level signal LVL.
Boost capacitance switch circuit
314
also has a capacitor Cb
1
connected between an internal node N
21
and the output node of an inverter IV
12
, and a boost capacitor Cb
2
connected between transistors Q
22
, Q
23
and internal node N
21
.
Voltage switch circuit
315
has a P type MOS transistor Q
24
having its gate connected to a node N
22
and provided to connect power supply line
342
and internal node N
21
, and a P type MOS transistor Q
25
and a N type MOS transistor Q
26
connected in series between internal node N
21
and ground line
344
. The gates of transistors Q
25
and Q
26
are connected to the output node of inverter IV
11
.
According to such a construction, when the output of inverter IV
11
is at the “H” level corresponding to an inactive state of boost control signal BST, voltage generation switch circuit
315
outputs power supply voltage Vcc to internal node N
21
. When the output of inverter IV
11
is at the “L” level corresponding to an activate state of boost control signal BST, however, transistor Q
24
turns off, internal node N
21
and power supply line
342
are thus disconnected, and the output voltage of boost capacitance switch circuit
314
is transmitted to output transistor
330
.
In boost capacitance switch circuit
314
, when boost control signal BST is inactive, and the output of inverter IV
11
is at the “H” level, the output of inverter IV
12
attains the “L” level and transistor Q
23
turns on, and therefore boost capacitor Cb
1
is charged by a voltage difference between power supply voltage Vcc and the “L” level voltage output from inverter IV
12
. Further, boost capacitor Cb
2
is charged by a voltage difference between power supply voltage Vcc and ground voltage Vss.
When the output of inverter IV
11
changes to the “L” level in response to activation of boost control signal BST, charge stored in both boost capacitors Cb
1
, Cb
2
or only charge stored in boost capacitor Cb
1
is discharged to internal node N
21
according to the voltage level of Vcc level signal LVL. Thus, the voltage level of internal node N
21
has a value of the “H” level voltage output from inverter IV
12
plus the boosted amount corresponding to the charge stored in one or more boost capacitors.
Vcc level signal LVL is set at the “L” level when power supply voltage Vcc is at most a prescribed level and at the “H” level when power supply voltage Vcc is higher than the prescribed level. When the output
Ho Hoai V.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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