Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-01-29
2001-05-15
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S749000, C438S750000, C438S753000, C438S754000, C438S756000
Reexamination Certificate
active
06232240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating a capacitor, and more particularly, relates to a method for fabricating a DRAM cell and simultaneously increasing capacitance of the capacitor as well as reducing step height between the periphery circuit region and the memory cell region of the DRAM cell.
2. Description of the Prior Art
For high density DRAMs, such as in the 1 GB DRAM and larger, the density of the memory cells is increased when compared with the low capacity DRAMs. A DRAM cell contains a memory cell array region and a periphery region. The memory cells are formed within the memory cell array region, and the periphery circuit is fabricated in the periphery region. The memory cell in the memory cell array region is basically composed of a transistor and a capacitor, which includes a storage node as a cubic electrode of the capacitor. Due to the high intensity of memory cell, and the structure of the storage node, the step height between the memory cell array region and the periphery region introduces a serious problem, such as exposure, alignment, and focus, in following processes that fabricating the DRAM.
In order to increase the charges stored in a capacitor, a stacked capacitor is developed, but there is a difference between the altitude of the stacked capacitor in a memory cell region and the altitude of the periphery region. As shown in
FIG. 1
, the cross-sectional view of a wafer shows that a memory cell region
10
and a periphery region
11
are on a substrate
12
. A first bit line
14
and a gate electrode
15
of a transistor are formed on the substrate
12
, in addition, a first dielectric layer
16
is formed on and between the first bit line
14
and the gate electrode
15
. Then a second bit line
20
and a third bit line
21
are formed on the cubic dielectric layer
16
, besides, a second dielectric layer
23
is formed on the second bit line
20
and the third bit line
21
. A third dielectric layer
24
is formed on topography of the wafer including the memory cell region
10
and the periphery region
11
, in addition, the second dielectric layer
23
between the second bit line
20
and the third dielectric layer
24
acts as an diffusion barrier layer. During fabricating a storage node
25
of the capacitor in the memory cell region
10
, the third dielectric layer
24
is etched and a first dielectric material is formed on the etched on the third dielectric layer
24
. The storage node
25
made of the first conductive material is a first electrode of the capacitor.
To fabricate an insulating film of the capacitor, the third dielectric layer
24
is partially removed to expose a cubic portion of the storage node. Refer to
FIG. 2
, the fourth dielectric layer
30
is formed on the exposed storage node
25
and on the etched third dielectric layer
24
, subsequently, a conductive layer
31
is formed on the fourth dielectric layer
30
. Then the fourth dielectric layer
30
and the conductive layer
31
are patterned to fit the necessary size. The patterned fourth dielectric layer
30
and the conductive layer
31
act as the insulating layer and the second conductive plate of the capacitor respectively. Thus the transistor is fabricated in the memory cell region
10
. To isolate the electricity of the capacitor composed of the fourth dielectric layer
30
, the conductive layer
31
and the underlying storage node
25
, a fifth dielectric layer
35
is formed on the topography of the wafer including the memory cell region
10
and the periphery region
11
.
After the capacitor is fabricated, proceed with the periphery region
11
to manufacture the periphery circuit in the periphery region
11
. So the periphery circuit mentioned above, the bit lines and the gate electrode
15
of the transistor are formed as shown in FIG.
3
. In addition, the periphery circuit mentioned above, the bit lines and the gate electrode
15
of the transistor are used to control the charge stored in the stacked capacitor. Due to the exposed portion of the stacked capacitor, as shown in
FIG. 3
, the altitude of the fifth dielectric layer
35
in the memory cell region
10
is higher than the altitude of the fifth dielectric layer
35
in the periphery region
11
. The altitude difference &agr; between the memory cell region
10
and the periphery region
11
of the prior art DRAM shown in
FIG. 3
is the step height between the memory cell region
10
and the periphery region
11
. Due to the step height &agr;, it is difficult to proceed with the periphery region
11
to form the periphery circuit in the periphery region
11
because of the problems such as focus problem raised from the step height &agr;.
SUMMARY OF THE INVENTION
Because the step height between the memory cell region and the periphery region in the prior art memory device is too large, many problems are raised from the large step height. In addition, the improvement of the effective surface area of the storage node in the prior art capacitor is necessary in fabricating a memory device in the trend of increasing density of integrated circuit.
One of the purposes of the present invention is to increase the effective area of the capacitor (the surface area of the storage node adjacent to the dielectric layer); thus the capacitance of the capacitor is increased. In addition, the other purpose of the present invention is to reduce the step height between the memory cell region and the periphery region of the memory device. So the problem raised from the step height is averted in the present invention.
A method for forming a memory device is disclosed herein, the method according to the preferred embodiment of the present invention includes the following steps. First, a bit line and a transistor are formed on a first region of a substrate. A portion of the first region of the substrate is between the bit line and the transistor. Then a transistor is formed on the first dielectric layer on the bit line, the transistor, and the exposed portion of the first region of the substrate. Subsequently, a second dielectric layer is formed on the first dielectric layer and a second portion of the substrate. Then a interface-etching step is used to etch the second dielectric layer to expose the portion of the first region of the substrate.
The next step is to form a storage node that contacting with the portion of the first region of the substrate within the second dielectric layer. The storage node includes a cubic portion connecting to the exposed portion of the first region of the substrate. The bottom of the cubic portion of the storage node faces the substrate. Then the second dielectric layer is etched to expose the surface including the bottom of the cubic portion of the storage node. In the step mentioned above, the effective area of the capacitor is increased. The next step is to form an insulating layer on the exposed surface including the bottom of the cubic portion of the storage node. Then form a conductive layer on the insulating layer, wherein the storage node, the insulating layer, and the conductive layer constitutes the capacitor within the first region of the substrate, besides, the capacitor is electrically coupled to the transistor.
Subsequently, form the periphery circuit within the second region of the substrate, the forgoing periphery circuit is used to control charges stored in the capacitor. Finally, form a third dielectric layer on the periphery circuit within the second region of the substrate, on the second dielectric layer within the second region of the substrate, and on the transistor within the first portion of the substrate. The altitude of the third dielectric layer within the second region of the substrate is higher than that of the bottom of the cubic portion of the storage node facing the substrate. The altitude of the third dielectric layer within the second region of the substrate is lower than the altitude of the third dielectric layer within the first region of the substrate. Thus the step height between the memory
Christensen O'Connor Johnson & Kindness PLLC
Kunemund Robert
Tran Binh X.
Vanguard International Semiconductor Corporation
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