Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
1998-04-08
2001-07-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S081000, C326S083000, C326S086000, C326S121000, C327S534000
Reexamination Certificate
active
06255850
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to integrated circuits, and more particularly, to protection from high voltages on integrated circuit input/output pins.
2. Description of the Related Art
Input/output (“I/O”) circuits are used to input electronic signals to and output electronic signals from integrated circuits. A typical integrated circuit (“IC”) includes an integral I/O circuit for each of its externally accessible I/O pins. An I/O circuit usually includes a driver circuit which receives signals from the IC and outputs them to the I/O pin. It also generally includes an input buffer which receives signals from the I/O pin and inputs them to the IC. A typical I/O circuit also includes an enable circuit which can place the driver circuit in either a high impedance state in which signals can be input to the IC via the I/O pin, or in an output enabled state in which signals can be output from the IC via the I/O pin.
I/O circuits transfer signals to and from integrated circuit devices in a variety of types of electronic systems. For instance, I/O circuits may be used to interconnect integrated circuits to a shared system bus so that multiple ICs connected to the bus can communicate with each other. In many electronic systems all of the integrated circuits connected to a system bus operate at the same supply voltage level. However, as the dimensions of the circuits in ICs have decreased, the supply voltages employed by ICs also have decreased. As a result, there has been a proliferation of mixed signal systems in which some ICs connected to a system bus operate at a higher supply voltage (e.g., 5-volts), and other ICs connected to the same system bus operate at a lower supply voltage (e.g., 3.3-volts).
A problem with mixed signal systems has been the occurrence of leakage currents, over the system bus, from an IC operating at a higher supply voltage to an IC operating at a lower supply voltage. For instance, an IC operating with a 3.3 volt supply may experience an overvoltage when an IC connected to the same bus as the 3.3 volt device drives a 5 volt signal onto the bus. An IC may experience an overvoltage, for example, when the voltage on one of its I/O pins is greater than the IC's internal supply voltage. As used herein, an IC's internal voltage includes both core and peripheral supply voltages, which may have the same or different values. Thus, leakage current may result when an output level high signal is imparted from one IC onto an I/O pin of another IC operating at a lower supply voltage.
The illustrative drawing of
FIG. 1
shows a pull-up/pull-down driver circuit which will be used to explain such leakage currents. The driver circuit includes a pull-up driver
110
and a pull-down driver
115
. In this example, pull-up driver
110
is a p-channel (PMOS) transistor, and pull-down driver
115
is an n-channel (NMOS) transistor. Pull-up driver
110
is coupled between a supply voltage
117
and a pin (or pad)
120
. Pin
120
is referred to as an I/O pin as it may be used for input or output, or both. Pull-down driver
115
is coupled between pin
120
and a supply voltage
122
. Supply
117
is typically VDD or VCC and supply
122
is typically VSS.
In operation, the output buffer will generate a logic high, logic low, or be tristated (i.e., high impedance state) depending on the logic signals at PU and PD. PU is provided to a gate of pull-up driver
110
, and PD is provided to a gate of pull-down driver
115
. When PU is a low and PD is a low, the pull-up drive
110
is on and the pull-down driver
115
is off, and the pin will be driven high (to the level of VCC). When PU is high and PD is high, the pull-up driver
110
is off and the pull-down driver
115
is on, and the pin will be driven low (to the level of VSS). When PU is high and PD is low, both the pull-up driver
110
and the pull-down driver
115
are off, and the pin
120
will be tristated. Pin
120
is typically also coupled to an input buffer (not shown) for the inputting of logical signals into the integrated circuit and the core. Pin
120
may be used as an input when the output buffer is placed in tristate, or may also be used to feed back signals from the output buffer into the integrated circuit.
However, the driver circuit shown in
FIG. 1
is not tolerant to high voltages, and may not be useful in the case where input voltages are imparted by an integrated circuit having a supply voltage above a level of the first supply voltage
117
. For example, when the output buffer is tristated, signals are input to the input buffer (not shown) via pin
120
. If first supply
117
is 3.3 volts, then when interfacing a 5-volt integrated circuit, pin
120
may potentially be 5 volts or above. A 5-volt input would represent a logic high input. This voltage may even go above 5 volts during transitions due to overshoots. This poses potential problems.
An I
1
current sneak path (or leakage path) may occur when the VPIN (the voltage level at the pin) goes above 3.3 volts+|VTP|. VTP is the threshold voltage of pull-up driver
110
. Furthermore, in an embodiment, pull-up driver
110
is a PMOS transistor and formed in an n-well on a p-type substrate. In that case, there may be a parasitic diode
130
between pin
120
and first supply
117
. Parasitic diode
130
represents the diode between the p-diffusion used to form the drain and the n-well region, which is connected to the first supply voltage
117
. Therefore, an I
2
current sneak path will also occur when the VPIN goes above 3.3 volts+Vdiode. Vdiode is the turn-on or forward voltage (VF) of the diode.
Leakage current paths I
1
and I
2
represent a DC (direct current) path which can cause the first supply (VCC) to rise. If VCC rises above maximum allowable levels and remains at those levels for longer than an acceptable time, the device may have oxide reliability issues. One solution to the problem of leakage currents in mixed signal systems is to provide voltage overshoot protection that blocks the flow of leakage current in overshoot situations.
Some examples of solutions to current leakage problems resulting from voltage overshoot on I/O pins are proposed in the following patents: U.S. Pat. No. 5,151,619, entitled, “CMOS Off Chip Driver Circuit”, issued to Austin, et al.; U.S. Pat. No. 5,450,025, entitled, “Tristate Buffer For Interfacing to a Bus Subject to Overvoltage Conditions”, issued to Shay; U.S. Pat. No. 5,396,128, entitled, “Output Circuit For Interfacing Integrated Circuits Having Different Power Supply Potentials”, issued to Dunning, et al.; U.S. Pat. No. 5,467,031, entitled, “3.3 Volt CMOS Tri-State Driver Circuit Capable of Driving Common 5 Volt Line”, issued to Nguyen, et al.; and U.S. Pat. No. 5,546,019, entitled, “CMOS I/O Circuit With 3.3 Volt Output And Tolerance of 5 Volt Input”, issued to Liao.
The Peripheral Component Interconnect (PCI) system architecture is an example of an architecture that imposes specific requirements upon I/O circuits that are quite different from the typical requirements in mixed signal systems. For instance, a requirement of a typical PCI system in a 3.3 volt environment (a system environment in which all ICs connected to the system bus have a 3.3 volt supply), calls for integrated circuits with I/O circuits that include internal termination which can sink current from a PCI system bus to the individual ICs'3.3 volt supplies. Typically, this PCI system architecture requirement is satisfied by an internal clamp circuit which includes a clamping diode which provides a current sink path from an IC's I/O circuit to its internal supply voltage. A purpose of this requirement, for example, is to sink current in order to quickly dissipate ringing voltage overshoot excursions on an I/O pin.
From a practical standpoint, it is desirable for ICs to be built to be useable in either a mixed signal system or a PCI system or in both simultaneously, for example. Unfortunately, as explained above, the performance requirements of these
Altera Corporation
Cho James H.
Morrison & Foerster / LLP
Tokar Michael
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