Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-31
2001-05-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06230299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to EDA tools for parasitic extraction in the process of designing sub-micron integrated circuit.
2. Background Information
The technology of large scale integration continues to advance rapidly. Integrated circuits (IC) fabricated employing deep sub-micron processes are increasingly common and increasingly complex. One of the challenges faced by today's deep sub-micron IC designers is the issue of parasitic effects of passive interconnect. Deep sub-micron IC designers have come to recognize that these effects cannot be ignored, else the design can fail. These effects play an important role in timing, power, reliability as well as noise performance. In order to take parasitic effects of passive interconnect into consideration in post layout analysis for timing, power, etc., it is necessary to create electrical models for the physical connections present between the various devices in a deep sub-micron IC design, a process known as parasitic extraction. Multiple parasitic extractions performed repeatedly at different points in time to create multiple electrical models for different views of the design are often required.
With respect to parasitic extraction for deep sub-micron IC designs, conventional EDA tools typically suffer from at least four disadvantages:
(a) They do not support enough rich models to describe the increasingly complex processes;
(b) They do not adequately address electrical interdependence between a physical net model and a design model;
(c) They are incapable of dealing with the enormous data volumes generated by the increasingly complex sub-micron designs; and
(d) They do not efficiently support concurrent use by multiple post-layout analysis tools.
Thus, a more effective and yet efficient approach to extracting and storing connectivity and geometrical data for a deep sub-micron IC design that are comprehensive and organized to meet the needs of parasitic extraction is desired.
SUMMARY OF THE INVENTION
A data extraction tool is provided to extract filtered connectivity and geometrical data for specified layout cell hierarchies of an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The connectivity and geometrical data for each layout cell hierarchy are extracted at least in part in accordance with specified parasitic effect windows. In one embodiment, the data extraction tool includes a filtered extraction function (FEX) that operates to extract connectivity and geometrical data for layout nets of a layout cell hierarchy of the IC design, one or more layout nets at a time. The connectivity and geometrical data for each layout net are extracted at least in part in accordance with specified parasitic effect windows of layout layers of the specified layout cell hierarchy.
Additionally, one or more filtered databases (FDB) are provided to store the filtered connectivity and geometrical data of the layout cell hierarchies. In one embodiment, one FDB is employed for each layout cell hierarchy, and the filtered connectivity and geometrical data are indexed by layout nets of the layout cell hierarchy.
REFERENCES:
patent: 5896300 (1999-04-01), Raghavan
patent: 5999726 (1999-12-01), Ho
patent: 6006024 (1999-12-01), Guruswamy
McSherry Michael C.
Nguyen Paul M.
Strobel Richard E.
Todd Robert A.
Columbia IP Law Group, LLC
Do Thuan
Mentor Graphics Corporation
Smith Matthew
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