DRAM memory cell and array having pass transistors with...

Details DRAM memory cell and array having pass transistors with... DRAM memory cell and array having pass transistors with...

1999-02-01

2001-03-27

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000, C257S623000, C257S306000

Reexamination Certificate

active

06207985

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices, and more particularly to dynamic random access memory (DRAM) storage cells and arrays.
BACKGROUND OF THE INVENTION
As the complexity and power of computing systems increases, the amount of memory required for systems has also increased. This has resulted in the drive for semiconductor memory devices of increased storage capacity. At the same time, the desire for more efficient manufacturing and more compact electronic devices has led to the competing interest of shrinking semiconductor memory devices to as small a size as possible. As a result, there is a continuous drive to arrive at semiconductor memory devices which have as high a density (data bits per physical area) as possible.
A common type of semiconductor memory device is the dynamic random access; memory (DRAM). DRAMs typically include a large number (millions or thousands) of memory cells, each of which can store at least one bit of data. The memory cells are usually arranged into an array configuration of rows and columns. Because the primary function of DRAM is to store data, the DRAM array makes up the majority of the area on a DRAM. Thus, any reduction in the size of a memory cell translates into increased memory density.
While density is an important features of a DRAM, another factor, speed, is also important. One reason for the increase in system computing power is the faster speeds at which such systems operate. For this reason, it is also desirable to provide a DRAM that has a fast operating speed, so that data can be provided to a system at a sufficient rate.
DRAMs are a preferred choice for main system memory as they are typically less costly than other memory types and consume relatively low amounts of power. However, because DRAMs are being used more often in battery operated applications, such as laptop computers, further improvements in power consumption are desirable. Lower power DRAMs can contribute to longer battery lifetimes in battery operated systems.
To better understand the factors involved in DRAM design that impact memory device density, speed and power consumption, the architecture of a conventional DRAM memory array will be reviewed. A typical DRAM array includes memory cells arranged in row and columns, with the memory cells of the same row being commonly coupled to a word line and the memory cells of the same column being commonly coupled to a bit line.
The data stored within the memory cells is accessed according to various DRAM operations which include read operations, write operations and refresh operations. Read and write operations usually begin with the application of an external memory address. Commonly, an applied memory address is multiplexed, with a row address being applied first, and a column address being applied subsequently. The application of the row address results in the activation of a word line. Once activated, the word line couples the data stored within its respective row to the bit lines of the array. The coupling of a row of memory cells to bit lines results in differential voltage signals appearing on the bit lines (or bit line pairs). The differential signals are relatively small, and so must be amplified (typically by a sense amplifier). The application of the column address activates column decoder circuits, which connect a given group of bit lines to input/output circuits.
Referring now to
FIG. 1
, a prior DRAM array is set forth and designated by the general reference character
100
. The DRAM array
100
is arranged as an n×m array, having n rows coupled to n word lines (WL
0
-WLn) and m columns coupled to m sets of bit line pairs (BL
0
, BL
0
_-BLm, BLm_). A memory cell is formed where a word line intersects a bit line pair. The memory cells are designated as M
00
-Mnm, where the first digit following the “M” represents the physical row of the memory cell's location and the second digit represents the physical column of the memory cell's location. For example, M
00
is the memory cell located at the intersection of WL
0
and bit line pair BL
0
/BL
0
_.
The word lines of the DRAM array
100
are driven by a word line driver bank
102
coupled to the word lines (WL
0
-WLn). The word line driver bank
102
is separated into n separate word line driver circuits, shown as DRV
0
-DRVn. The word line driver bank
102
is responsive to a row address (not shown) in such a manner that only one word line driver circuit (DRV
0
-DRVn) will drive its corresponding word line high, when the row address is received. For example, word line driver circuit DRV
0
will drive word line WL
0
high when the row address value of “zero” is received, and word line driver circuit DRVn will drive word line WLn high when the row address value of “n” is received.
The DRAM array
100
further includes a sense amplifier bank
104
coupled to the bit line pairs (BL
0
, BL
0
_-BLm, BLm_). The sense amplifier bank
104
is separated into m separate sense amplifier circuits, shown as SA
0
-SAm. While all of the sense amplifiers
104
will be activated simultaneously, only selected of the sense amplifiers (SA
0
-SAm) will pass sensed data to the DRAM outputs (not shown). A sense amplifier (SA
0
-SAm) will be selected according to a column address applied to a column decoder (not shown) in the DRAM.
The typical DRAM memory cell stores data by placing charge on, or removing charge from, a storage capacitor. Once a storage capacitor has been initially charged, over time, the amount of charge will be reduced by way of a leakage current. Thus, it is important for the DRAM to restore the charge on the capacitor before the amount of charge falls below a critical level, due to leakage mechanisms. The critical level of charge for a storage capacitor arises out of the minimum sensitivity of the DRAM sense amplifiers. The storage capacitor must have enough charge to create a sufficient differential voltage on the bit lines for the sense amplifier to reliably sense. The time needed before the charge on the capacitor falls below the critical level is commonly referred to as the maximum “pause” period.
Typically, the restoration of charge within a DRAM memory cell is accomplished with a refresh operation. Thus, a DRAM should perform a refresh operation on every row in the device before that row experiences the maximum “pause” period. The refreshing operation of a DRAM is considered important as such operations consume a relatively large amount of power because all the bit lines in an array must be driven to refresh the memory cells in a row. One way to reduce power consumption in a DRAM, therefore, is to reduce the rate of charge leakage from the storage capacitor. By doing so, the maximum pause period of the DRAM can be increased, allowing refresh operations to occur with less frequency.
Referring once again to
FIG. 1
, each memory cell (M
00
-Mnm) of the DRAM array
100
is shown to contain a pass transistor (shown as n-channel MOSFETs Q
00
-Qnm) and a storage capacitor (shown as C
00
-Cnm). Within each memory cell (M
00
-Mnm) the junction of the source of the each storage capacitor (C
00
-Cnm) and its associated pass transistor (Q
00
-Qnm) is shown as a storage node (
106
-
112
). The potential at the storage node will determine the logic of the data stored within the memory cell. Thus, a memory cell (M
00
-Mnm) is accessed in a read, write and refresh operation by coupling its storage node (
106
-
112
) to its respective bit line (BL
0
, BL
0
_-BLm, BLm_.
In a read cycle, the bit line pairs (BL
0
, BL
0
_-BLm, BLm_) are initially at a precharge potential. This potential is typically midway between a logic high and logic low. Thus, assuming Vss=0 volts, the bit lines would be precharged to Vcc/2. The read cycle begins with a row address being applied to the DRAM to activate a word line. The pass transistors in a row of memory cells are turned on, coupling their storage nodes to their respective bit lines (BL
0
, BL
0
_-BLm, BLm_. In order to ensure that maximum charge is placed on the bit lines, th

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