Electricity: measuring and testing – Plural – automatically sequential tests
Reexamination Certificate
1999-07-26
2001-09-18
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Plural, automatically sequential tests
C324S763010
Reexamination Certificate
active
06291978
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of circuit board testing. More specifically, the invention relates to a system and method for digitally testing for shorts, opens and connected nodes on printed circuit boards using automatic test equipment.
2. Background Art
Testing complex digital circuitry at the circuit board level is frequently performed on an Automated Test Equipment (ATE) system. The HPFTS40 functional test system, available from Hewlett Packard Company, Palo Alto, Calif., is an example of such an ATE system. The preferred embodiment of the present invention is implemented using the HPFTS40.
Testing performed on an ATE system includes functional test and in-circuit test. Functional test conventionally involves providing input signals to the external inputs of a circuit board or printed wiring board (PWB) under test and observing output signals from the external outputs of the PWB. This type of testing becomes quite complex for large circuits and generally provides limited diagnostics. Both in-circuit testing and functional testing on ATE systems enables nodes on a printed circuit board to be tested for short circuits, open circuits, interconnects or other manufacturing or device defects, by driving selected nodes on the circuit board and observing the response at other nodes. In-circuit testing entails utilizing contact probes which can contact internal nodes on the circuit board. Signals are applied to and received from the board via these probes. Detailed diagnostics are available from in-circuit testing. Functional testing is normally performed from an edge connector on the circuit board.
Both functional and traditional digital in-circuit testing require that power be applied to the board being tested. Applying power, however, can damage components if short circuits are present. Therefore, it is desirable to perform a low power shorts test to detect and correct short circuits and other misconnections prior to subjecting the board to full power.
Interconnect tests can be performed as part of either a functional test or an in-circuit test. Interconnect tests seek to locate problems which are introduced during mounting of the integrated circuit (IC) chips on the PWB. An interconnect test involves testing each conductive “net” or “node” on the PWB to ensure that it connects the proper devices (for example, input and/or output buffers of one or more IC chips). A “net” or “node” is defined as an equipotential surface formed by a physical conductor. The primary problems that are tested for are open-circuits and short-circuits. Open-circuits frequently result from broken pins or “cold” solder joints. Short-circuits may be caused by excess solder bridging the gap from one IC pin connection to the next.
Historically, in-circuit and/or functional testing on an ATE system enables nodes on a printed circuit board to be tested for short circuits by driving the nodes on the circuit board with analog instruments. Analog instruments allow low voltages to be used to drive the circuit board pins, or nodes, and accurate measurements can be made. Typically an analog measurement is less susceptible to noise errors because measurement can be accomplished using a long integration cycle. The problem with analog testing is that signal throughput is slow. Digital testing can significantly improve signal throughput. The cost of utilizing digital signals is that measurements made utilizing long integration cycles are not possible because of the step-like characteristic of digital signals. Therefore errors are more prevalent. Attempts have been made to use digital signals when performing functional testing of circuit boards. However, special equipment has been required to reduce signal errors. Such special equipment includes damped drivers and receivers with filters. This special equipment adds cost and size to the testing system. Even utilizing such special equipment, digital shorts testing has not achieved satisfactory results.
What is needed is a system and method for performing low powered interconnect tests with increased throughput for test signals in an automatic test environment without requiring specialized equipment, while maintaining the accuracy associated with traditional analog test systems.
SUMMARY OF THE INVENTION
The present invention is a system and method for performing interconnect testing on a circuit board containing a plurality of pins or nodes. The circuit board testing system has a testhead containing a plurality of test channels, each test channel is configured for coupling with one of the nodes. The circuit board testing system includes a driving means, a receiving means, a switch means and a controlling means for controlling the driving means. The driving means produces a digital signal having a predetermined value. The driving means is calibrated to minimize signal error. The receiving means receives a signal from the driving means and trips high or low at a predetermined value. The receiving means is also calibrated to minimize signal error. Each testing means has a switch means. The switch means can couple a node to ground, or zero potential.
The method of the invention is for testing the interconnection of a plurality of nodes on a circuit board utilizing an automated test system having a plurality of testing channels. Each testing channel includes a digital driver, a digital receiver, a ground switch, and a test probe configured to contact one of the. plurality of nodes on the circuit board. The present invention calibrates each digital driver to precisely output a first predetermined signal voltage then calibrates each digital receiver to trip at a second predetermined signal voltage. After calibrations the present invention performs an interconnect test on the circuit board. The interconnect test comprises selecting a test group of nodes and identifying the classification of the test group from a node classification library. Based upon this classification one of three tests are performed on the test group. The three tests are: (1) a grounded test, to test if a node is shorted to ground or zero potential; (2) a connection test, to test if all nodes in said test group are connected together; and (3) an isolation test, to test if a node is isolated from all other nodes.
An advantage of the present invention is an increased signal throughput during interconnect testing.
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Alcorn Barry A.
Boswell Bryan D.
Chandler Kevin G.
Heumann John M.
Schlotzhauer Ed O.
Agilent Technologie,s Inc.
Leroux E P
Metjahic Safet
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