Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Utility Patent
1999-04-14
2001-01-02
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S784000, C257S781000, C257S703000, C257S697000, C257S677000, C438S615000, C438S613000, C438S617000, C438S612000
Utility Patent
active
06169330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of metal fusion bonding, and more specifically this invention provides for the low cost thermosonic bonding, or fusing, of a gold-coated semiconductor-chip to a gold-coated chip-carrier substrate member, wherein the two mating gold coatings, on the semiconductor-chip and the substrate member respectively, each comprise a continuous film of gold.
2. Description of the Related Art
Solid state high temperature electronic devices have been made from a wide variety of bandgap semiconductor materials, such as SiC and Ga
x
Al
1−x
N. These high temperature electronic devices may be three electrode devices, such as transistors, or thyristors, rectifiers, Integrated Circuits (ICs), detectors, etc., and electronic devices of these types may include components, such as capacitors, inductors and resistors that are suitable for high temperature operation.
High temperature semiconductor devices are usually physically packaged using a material(s) whose thermal expansion coefficient (TEC) matches the TEC of the semiconductor device being packaged. This generally external packaging material maybe an electrically insulating material, such as a potting material, AlN, SiC, a ceramic, or a ceramic that is a combination of AlN and SiC.
The semiconductor device usually comprises both a semiconductor-chip, or chip-portion, and a chip-carrying substrate or substrate-portion on which the semiconductor-chip is physically mounted. The chip-carrying substrate is usually provided with metallized areas of some type to which the semiconductor-chip's input/output/power electrodes, and perhaps other external leads, or wires, are connected. Such a metallization material may be applied to these areas of the chip-carrying substrate by an evaporation process, a sputtering process, a plating process, or a printing process. Suitable metallization materials include tungsten, nickel, titanium, molybdenum, and noble metals such as Au and Pt.
Ultrasonic bonding is generally known, as is shown by the following representative examples. U.S. Pat. No. 4,534,811 provides for the bonding of two elements by the use of laser-heat and an ultrasonic vibrating force. U.S. Pat. No. 4,674,671 teaches the bonding of fine aluminum, gold or palladium wires using ultrasonic energy and pressure. U.S. Pat. No. 4,842,662 describes the bonding of a lead to an IC chip by the use of gold bumps that are located between the lead and a platinum/titanium film that is carried by the IC chip. The use of heat, ultrasonic oscillation, and mechanical pressure is mentioned. U.S. Pat. No. 4,970,365 teaches bonding gold-coated leads to copper pads by the use of a bonding tip, laser-heat, static force, and ultrasonic energy. Gold-to-gold interface bonding is also mentioned. U.S. Pat. No. 5,186,378 describes forming a microelectronic bond by the use of heat and an ultrasonic transducer. U.S. Pat. No. 5,240,166 describes a thermally enhanced ultrasonic bonding tool having a thin film resistor disposed on the tool's bonding tip.
Yet other examples of bonding are found in U.S. Pat. Nos. 3,387,365, 3,480,492, 3,628,716, 4,312,117, 4,903,883, 5,326,014, and 5,364,009.
U.S. Pat. No. 5,341,979 to Gupta is of interest in that it describes the use of an ultrasonic/thermosonic coil and control apparatus 50 to bond a substrate 35 to a semiconductor die 10. As shown in FIGS. 1-4, semiconductor die 10, which is formed from a gallium arsenide substrate (col 2, lines 59-63), includes an active semiconductor device 11 that may be a MOSFET, JFET, BJT, etc (col 2, lines 63-67). Bonding pads 14,15,17 are provided on die 10. Bonding pads 14,15 are multi-layer nickel, germanium, tungsten, nickel and gold, wherein nickel contacts the major surface 12 of die 10 (col 3, lines 10-14). As shown in FIG. 5, gold hour-glass shaped bumps 30 are provided to thermosonic bond pads 14,14,17 of die 10 to contact pads 44,46,47 on substrate 35 (col 5, line 61, to col 5, line 17). The Patent suggests a bonding temperature range of less than about 180° C. (col 5, lines 44-46), a force equivalent to a mass ranging between about 50 grams and 1,500 grams (col 5, lines 65-68), and a range of movement of thermosonic tool/end-effector 52 (col 6, lines 1-10).
While methods and apparatus as described above are generally useful for their limited intended purposes, the need remains in the art for a method and apparatus that provides for bonding a semiconductor-chip to an underlying chip-carrier or substrate, wherein the final packaged semiconductor-chip/chip-carrier assembly is capable of withstanding high operating temperatures, wherein the bonding method/apparatus is reliable and repeatable, and wherein the required bonding can be provided at a relative low cost.
SUMMARY OF THE INVENTION
This invention provides a semiconductor assembly wherein a semiconductor-chip is bonded to a chip-carrier substrate by way of a gold-to-gold bonding interface. In the method of this invention, a vacuum chuck physically holds the semiconductor-chip in physical contact with the chip-carrier substrate, as static force, ultrasonic power, and an elevated temperature are applied to two mating gold surfaces that are formed by two continuous and physically mating gold layers. The finished bonded assembly is encased in a potting ceramic, or the finished bonded assembly is encased in a housing that includes a transparent cover that enables use as an optoelectronic semiconductor device. This cover may comprise single crystal AlN, sapphire, and/or a UV transparent material.
An object of this invention is to provide an AlN substrate member whose generally flat upper surface includes a first, a second, and a third physically spaced, upward facing, and continuous gold layer thereon. The first and second gold layers are located at a border area of the substrate member. The third gold layer has a first minor portion that is located at the border area of the substrate member, adjacent to the first and second gold layers. The third gold layer also includes a second major portion that is formed integrally with the first minor portion, this second major portion being located inward of the border area of the substrate member.
A first, second and third, gold-coated, flat-surface, tungsten pin have their flat surfaces, respectively, gold-to-gold bonded to the first gold layer, the second gold layer, and the first minor portion of the third gold layer. These first, second and third gold-coated tungsten pins each have an end that extends beyond the border area of the substrate member. These pins are adapted for mounting are attaching the substrate member to a related device, such as a socket or the like.
A high temperature, three-electrode, SiC and GaN-based, semiconductor chip is provided having a generally flat bottom gold surface that comprises a first gold electrode having an upper surface with a second gold electrode thereon, and having a third gold electrode thereon.
The bottom gold surface of the semiconductor chip is gold-to-gold bonded to the second major portion of the third gold layer that is on the substrate member, this bonding taking place in the presence of static force, ultrasonic energy, and an elevated temperature.
A first gold wire connects between the upper-surface of the semiconductor chip's second gold electrode and the substrate's first gold layer. A second gold wire connects between the upper-surface of the semiconductor chip's third gold electrode the substrate's second gold layer. These connections are made by virtue of gold-to-gold bonding.
As a feature of the invention, an electrically insulative paste is provided to cover and seal the upper surface of the chip/substrate/wire assembly in a manner to leave the extending ends of the gold-coated tungsten pins exposed.
As an additional feature of the invention, an optoelectronic semiconductor chip device is provided and an electrically insulative housing provides an optically transparent cover, an AlN cover, a sapphire cover, or a UV transparent c
Astrulux, Inc.
Hancock Earl C.
Holland & Hart LLP
Sirr Francis A.
Thai Luan
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