Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-10-28
2001-01-09
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S528000, C438S163000, C257S347000
Reexamination Certificate
active
06171889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed to a semiconductor device and a method of manufacturing the same, especially to a semiconductor device with a SOI (silicon-on-insulator) structure and its manufacturing method.
2. Description of the Background Art
FIG. 23
is a sectional view showing NMOS and PMOS transistors
24
,
25
formed on a SOI substrate, as one of examples of the semiconductor device with the SOI structure.
With reference to
FIG. 23
, a buried oxide film
2
is formed on the main surface of a silicon substrate
1
, and a single-crystal silicon layer
3
(hereinafter referred to as a SOI layer) is formed on the buried oxide film
2
. With the SOI layer as a substrate, the NMOS and the PMOS transistors
24
,
25
are formed thereon.
The NMOS transistor
24
includes a pair of source/drain layers
35
b
independently formed parallel to each other at the surface of the SOI layer
3
, and a pair of lightly doped drain layers
35
a
(hereinafter referred to as LDD layers) formed adjacent to the facing edges of the source/drain layers
35
b.
A gate oxide film
30
is formed on the SOI layer
3
, and a gate electrode
28
is formed on the gate oxide film
30
. Further, sidewall oxide films
26
are formed at the side surfaces of the gate oxide film
30
and the gate electrode
28
.
The PMOS transistor
25
includes a pair of source/drain layers
36
b
independently formed parallel to each other at the surface of the SOI layer
3
, and a pair of LDD layers
36
a
formed adjacent to the facing edges of the source/drain layers
36
b.
The gate oxide film
30
is formed on the SOI layer
3
, and the gate electrode
28
is formed on the gate oxide film
30
. Further, the sidewall oxide films
26
are formed at the side surfaces of the gate oxide film
30
and the gate electrode
28
.
The NMOS and the PMOS transistors
24
,
25
are electrically isolated by an isolation oxide film
40
formed so as to reach to the buried oxide film
2
from the surface of the SOI layer
3
. The isolation oxide film
40
isolates the NMOS and the PMOS transistors
24
,
25
from other elements as well.
FIG. 23
also shows that high-concentration impurity regions
130
are formed in contact portions between the isolation oxide film
40
and the SOI layer
3
on which the NMOS transistor
24
is to be formed.
As described above, the NMOS and the PMOS transistors
24
,
25
formed on the SOI substrate have structures with the SOI layer
3
, which is to be a channel, held between the gate oxide film
30
and the buried oxide film
2
. Thus, the SOI layer
3
is inferior in crystalline to a bulk silicon substrate, and further is formed thin as is evident from FIG.
23
.
Further, into such SOI layer
3
, impurity ions are generally implanted in a manufacturing processes, such as channel implantation and source/drain implantation, of the NMOS and the PMOS transistors
24
,
25
. This gives damage to the SOI layer
3
and causes further deterioration in cyristalline. Thus, a transistor formed on the SOI substrate is inferior in transistor characteristics to that formed on the bulk silicon substrate.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device formed on a SOI substrate in which a buried oxide film and a SOI layer are stacked on a silicon substrate. The semiconductor device comprises: a first semiconductor region of a first conductivity type formed in a predetermined position of the SOI layer, ranging from a surface of the SOI layer to a surface of the buried oxide film; a pair of second semiconductor regions of a second conductivity type independently and selectively formed in the surface of the SOI layer so as to sandwich the first semiconductor region; a gate oxide film formed in an upper portion of the first semiconductor region; and a gate electrode formed on the gate oxide film, wherein the first semiconductor region contains nitrogen introduced so as to have a predetermined concentration distribution in a depth direction thereof, the predetermined concentration distribution having: a first peak portion protruding with a first concentration, in the vicinity of an interface between the first semiconductor region and the buried oxide film; and a second peak portion protruding with a second concentration, in the vicinity of an interface between the first semiconductor region and the gate oxide film.
Preferably, according to a second aspect of the present invention, the predetermined concentration distribution has a plane portion of near uniformity with a third concentration lower than the first and the second concentrations, in a region held between the first and the second peak portions.
Preferably, according to a third aspect of the present invention, the first concentration ranges from 1×10
18
to 1×10
19
/cm
3
; the second concentration ranges from 1×10
19
to 1×10
20
/cm
3
; and the third concentration ranges from 1×10
16
to 1×10
17
/cm
3
.
Preferably, according to a fourth aspect of the present invention, the predetermined concentration distribution has a third peak portion protruding with a third concentration at least lower than the second concentration, near a center of a region held between the first and the second peak portions.
Preferably, according to a fifth aspect of the present invention, the first concentration ranges from 1×10
18
to 1×10
19
/cm
3
; the second concentration ranges from 1×10
19
to 1×10
20
/cm
3
; and the third concentration ranges from 1×10
18
to 5×10
19
/cm
3
.
Preferably, according to a sixth aspect of the present invention, the second semiconductor region contains nitrogen introduced so as to have nearly the same concentration with the second concentration.
A seventh aspect of the present invention is directed to a method of manufacturing a semiconductor device formed on a SOI substrate in which a buried oxide film and a SOI layer are stacked on a silicon substrate. The method of manufacturing the semiconductor device comprises the steps of: (a) preparing the SOI substrate; (b) defining a device forming region for forming the semiconductor device by electrically isolating a predetermined region of the SOI layer from other regions; (c) forming a first semiconductor region of a first conductivity type by ion-implanting an impurity of a first conductivity type and nitrogen into the device forming region; (d) giving heat treatment to the first semiconductor region in such a condition that the nitrogen gets a predetermined concentration distribution in a depth direction of the first semiconductor region; (e) forming a gate oxide film on the first semiconductor region; (f) forming a gate electrode on the gate oxide film; and (g) forming second semiconductor regions of a second conductivity type by ion-implanting an impurity of a second conductivity type and nitrogen into the first semiconductor region with the gate electrode as a mask, wherein the predetermined concentration distribution has: a first peak portion protruding with a first concentration, in the vicinity of an interface between the first semiconductor region and the buried oxide film; and a second peak portion protruding with a second 6 concentration, in the vicinity of an interface between the first semiconductor region and the gate oxide film.
Preferably, according to an eighth aspect of the present invention, the step (c) comprises a step of ion-implanting the nitrogen after ion-implanting the impurity of a first conductivity type.
Preferably, according to a ninth aspect of the present invention, the step (c) comprises a step of ion-implanting the impurity of a first conductivity type after ion-implanting the nitrogen.
Preferably, according to a tenth aspect of the present invention, the nitrogen is implanted at a dose of 0.1×10
12
to 100×10
12
/cm
2
at an energy of 20 to 35 keV.
Preferably, according to an eleventh aspect of the present invention, the step (d) comprises a step of performing annealing in nitrogen at
Ipposhi Takashi
Iwamatsu Toshiaki
Goodwin David
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Wilczewski Mary
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2440850