Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-09-24
2001-06-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S112000
Reexamination Certificate
active
06242952
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to domino logic technology, and are more particularly directed to hold time latch circuits, systems, and methods.
In many modern circuit applications, it is often desirable to increase operational speed. For example, in microprocessor design the circuits which make up speed-limiting portions or affect the speed of the microprocessor are constantly scrutinized and re-designed to increase the overall microprocessor speed. Increased speed increases performance and, therefore, permits more detailed and sophisticated processing capabilities in a shorter amount of time.
To increase the speed of microprocessors, as well as other circuits where speed is important, domino logic transistor circuits are currently used because they often provide increased speed as compared to static logic transistor circuits. A domino logic circuit is characterized by operating in two phases. First, a precharge node is set to a first potential during a precharge phase. Second, during an evaluate phase, if the logic condition represented by the circuit is satisfied, the precharged node is discharged, thereby changing the logic output of the circuit. In other words, at the conclusion of the precharge phase, the precharged node causes a first logic state to be output by the domino logic circuit. Thereafter, if the precharged node is discharged during the evaluate phase, the output of the domino logic circuit represents a second logic state differing from the first logic state. Moreover, the act of discharging to change states, when accomplished using one or more n-channel transistors to gate the transition from precharge to discharge, represents a speed increase over the prior operation of static circuits which in one instance accomplished a transition with a network of n-channel transistors while in another instance accomplished the opposite transition with a network of p-channel transistors.
One specific example of domino logic transistor circuits is known as a hold time latch, and is discussed in greater detail later. By way of introduction, the hold time latch generally follows the principles set forth above as characteristic of domino logic circuits. More particularly, during the precharge phase a first stage in the hold time latch precharges and correspondingly outputs a low voltage, and thereafter during an evaluate phase the first stage may output a high voltage if one or more logic conditions are satisfied. Further distinguishing the hold time latch from other domino circuits is that the hold time latch takes advantage of a delay in precharging the latch. Specifically, the hold time latch is connected to output a data signal to a subsequent domino logic stage, where the subsequent domino stage evaluates out of phase with respect to the hold time latch. Thus, when the first stage completes its evaluate phase, the subsequent stage then performs its evaluate phase based on the data from the hold time latch. Note, however, that at the same time the subsequent stage begins its evaluate phase, the first stage begins its precharge phase. By design, however, there is a slight delay of time from this point where the precharge phase begins, and even though the control signals have changed to cause the beginning of the precharge phase of the first stage of the hold time latch, the output of the hold time latch first stage from its preceding evaluate phase remains valid. It is during this time, known as the hold time, that the subsequent stage is typically able to trigger (i.e., evaluate) based on the valid data from the first stage. Consequently, data may propagate through this as well as similar connections without the need for complicated additional latching circuitry.
While the hold time latch is therefore beneficial in certain applications in the art, the present inventors have recognized that many newer circuit technologies require dual rail signals, or may otherwise provide situations that may benefit from a circuit that has a complementary output operation to the hold time latch. The present inventors have further recognized, however, that merely inverting each operation of a hold time latch will not produce a viable circuit for use in domino logic circuits. Specifically, recall from above that the output of the first stage of a hold time latch initially provides a low voltage, then conditionally rises to a high voltage (if logic is satisfied), and then returns to the low voltage. A strict complementary operation, therefore, would initially provide a high voltage, then conditionally fall to a low voltage, and then return to the high voltage. However, the present inventors further recognize that this operation is not compatible with a typical subsequent domino logic stage for various reasons, one of which is that the return of the complementary first stage to a high voltage would cause the subsequent domino logic to erroneously discharge. Accordingly, below the present inventors provide various embodiments to overcome any such incompatibility and thereby also provide the capability of a constrained complementary operating domino circuit referred to below as an inverting hold time latch.
BRIEF SUMMARY OF THE INVENTION
In the preferred embodiment, there is a domino logic circuit comprising a first phase domino logic circuit operable in a precharge phase and an evaluate phase. The first phase domino logic circuit comprises a precharge node operable to change states. The domino logic circuit also comprises a second phase domino logic circuit operable in a precharge phase and an evaluate phase, wherein the precharge phase and the evaluate phase of the first phase domino logic circuit are out of phase with respect to the precharge phase and an evaluate phase of the second phase domino logic circuit. Further, the second phase domino logic circuit comprises a precharge node operable to change states in response to the states of the first phase domino logic circuit. Each of the first and second phase domino logic circuits further comprises a coupling device which when conducting couples the precharge node to a precharge voltage during a precharge phase and a discharge path connected to the precharge node which when conducting couples the precharge node to a voltage different than the precharge voltage during an evaluate phase, wherein the discharge path comprises logic circuitry. The first phase domino logic circuit is operable such that the precharge node of the first phase domino logic circuit is charged to a first state during the precharge phase of the first phase domino logic circuit, and the precharge node of the first phase domino logic circuit conditionally changes to a second state during the evaluate phase of the first phase domino logic circuit. The second phase domino logic circuit is operable such that the state of the precharge node of the second phase domino logic circuit may change in the evaluate phase of the second phase domino logic circuit and in response to the first phase domino logic circuit only when the state of the precharge node of the first phase domino logic circuit did not change in an immediately preceding evaluate phase of the first phase domino logic circuit. Other circuits, systems, and methods are also disclosed and claimed.
REFERENCES:
patent: 4841174 (1989-06-01), Chung et al.
patent: 5892372 (1999-04-01), Ciraula et al.
patent: 5942917 (1999-08-01), Chappell et al.
patent: 6049231 (2000-04-01), Bosshart et al.
Bosshart Patrick W.
Landman Paul E
Brady III W. James
Cho James H.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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