ATA compatible adapter having a shadow register configured...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting

Reexamination Certificate

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Details

C710S010000, C710S046000, C710S047000, C710S072000

Reexamination Certificate

active

06275879

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the control of storage and other devices when connected to a computer system and, more particularly, to an ATA compatible adapter which automatically polls devices and which interrupts a host computer only when a device requires service.
BACKGROUND OF THE INVENTION
One of the most popular types of data storage devices used on computer systems of all types is termed an IDE or ATA device. The name derives from the interface standard used by the device in order to connect to a computer system. The ATA Standard is recognized on an industry-wide basis and is administered under the auspices of the American National Standards Institute (ANSI). By following the Standard, computer users can obtain devices from a variety of manufacturers with the assurance that they will inter-operate.
The ATA Standard has enabled storage device manufacturers to produce low cost, high performance products. There are several elements in a computer system which are required in order for an ATA device to operate. These are the ATA devices themselves (Device), a host adapter (Adapter), a cable that couples them together (Cable) and the host computer software driver (Driver) that controls the Devices in the flow of data to and from them. The Adapter can be a separate item connected to or built into the host system (Host). Up to two Devices may be attached to one Cable. The data and control path provided by the Adapter, using the protocols defined in the ATA Standard is often referred to as a Channel. Thus one Channel may control up to two Devices. There is nothing to preclude an Adapter from supporting several Channels.
Although the ATA Standard allows the attachment of two Devices on one Channel, it is limited by its current ability to perform tasks with respect to only Device at a time. To overcome this limitation, the Standard is being changed to allow commands to be sent to both Devices and/or multiple commands to be sent to the same Device. This allows commands to be queued and executed in a more efficient manner by both Devices.
If a Device finishes a command and requires service from the Host, it can request service by changing the state of an Interrupt line on the Channel. The ATA interface is defined in such a way as to allow only the currently selected Device to cause an interrupt on the Channel. To overcome this, the host Driver has to alternately select (Poll) each Device to allow the Devices a chance to indicate that they want service.
In conventional computer systems, Polling is achieved by the Driver in the Host performing a sequence of input/output instructions to change the Device currently selected and read the status of the Device. This has to be alternately performed on each Device on a Channel. In multiple-channel situations, the Host has to select Devices on each Channel; one at a time. This software Polling can either consume a great deal of processor time or must rely on some other form of Host interrupt (e.g., a timer interrupt) to only Poll periodically. In the later case, if the timer, if the timer interrupt has a long period, the disk response latency is greatly increased; if it has a short period the processing overhead is increased. Using either software Polling methods results in excessive use of the Hosts resources and results in an overall and satisfactory system performance.
SUMMARY OF THE INVENTION
The present invention is directed to a data communication system comprising a host computer and at least one data storage device, configured to communicate with the host computer in accordance with an ATA protocol. The data storage device includes a register configured to hold device selection information received from the host computer. An ATA compatible cable is coupled to the at least one data storage device, the cable including a plurality of address lines. An ATA compatible adapter circuit is coupled to the cable and is disposed between the cable and the host computer. The Adapter circuit includes a shadow register which is configured to intercept device select information sent by the host computer. The adapter evaluates the contents of the shadow register and forwards the contents to a selected data storage device.
In another aspect of the invention, the adapter includes means for periodically polling the selected data storage device in order to receive an interrupt therefrom. The adapter forwards the interrupt to the host computer such that the data storage device is isolated from the host computer. Additionally, the adapter recognizes command information issued by the host computer and is further able to differentiate between command information directed to a data storage device and command information directed to the adapter.
In a further aspect of the invention, a second data storage device is coupled to the cable with the second data storage device including a register configured to hold device select information received from the host computer. The device select information is a binary value written into a bit position of each register. The binary value takes on a first value in order to select the first data storage device and a second value to select the second data storage device. The adapter alternately selects the first and second data storage devices for periodically polling each alternately selected data storage device in order to receive an interrupt therefrom. The adapter forwards the interrupt to the host computer such that each data storage device is polled without host computer intervention.


REFERENCES:
patent: 5463752 (1995-10-01), Benhase et al.
patent: 5590336 (1996-12-01), Parry
patent: 5765040 (1998-06-01), Uno et al.
patent: 5802398 (1998-09-01), Liu et al.
patent: 5905885 (1999-05-01), Richter et al.
patent: 5920709 (1999-07-01), Hartung et al.
patent: 5996045 (1999-11-01), Lee et al.

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