Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1998-07-16
2001-01-09
Gossage, Glenn (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C713S400000, C713S503000, C370S516000, C370S503000
Reexamination Certificate
active
06173380
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit technology and to integrated circuits used in data communications technology. More particularly, the present invention relates to data communications integrated circuit devices and protocols for enabling the alignment, based on a single clock, of multiple channels of clock-data signals, such as, for example, those used in 100BASE-T4 Ethernet networks.
2. The Prior Art
In a data processing system, it is desirable to maintain synchronization between the data stream and a clock. It is also desirable for the data to have a known relationship to the clock—such as setup time and hold time. If the relationship between the data and the clock becomes unpredictable, the data processing system will generate errors.
In a simple electronic circuit, the data bus and clock line may run side by side through the entire circuit and remain fully synchronized. This is common in integrated circuits and printed circuit boards. However, there are many cases, depending on the transmission media, where it is not possible to run a clock line side by side with the data bus and maintain synchronization. These common media include twisted pair, optical fiber and disk drive heads. In these situations it is common practice in the art to encode the data stream with the clock information. The data and clock information will be encoded into a single stream, sent through the medium, and then separated on the other side of the medium. Separating the clock and data information from a single stream is known as clock-data recovery. An encoding/decoding algorithm is designed to ensure that the clock-data pair will be synchronized.
Often, clock-data recovery involves only one serial data stream and one clock. For example, in the common usage of an Ethernet 10BASE-T system, the clock-data stream is transmitted on one twisted pair and received on another. In this case, only one clock-data channel requires recovery.
Recent developments in data communications, however, have created the need for increasing the amount and speed of transmitted data. As the volume of data communicated increases, there is an increased desire for greater speed of transmission across a variety of media; more and more bits per second need to be transmitted and received. A major limitation preventing this increased speed is the reliability of data signals at high speed. As is known to those of ordinary skill in the art, speed of transmission over current cost-effective media is limited by reliability, therefore limiting the overall speed of data communications.
A promising response to this limitation has been the use of multiple parallel clock-data channels. Multiple parallel channels allow transmission in parallel over multiple carriers rather than in series over a single transmission medium. The transmission speed is then approximately the product of the single channel rate and the number of multiple channels. As will be apparent to those of ordinary skill in the art, this allows a much higher transmission rate over conventional media. For example, with the advent of Fast Ethernet and other new communication protocols, multiple twisted pairs are widely used for achieving higher speeds.
One version of Fast Ethernet uses 100BASE-T4 technology, which transmits and receives clock-data information on three twisted pairs using a specific data coding scheme known as 8B6T coding. By transmitting on three twisted pairs simultaneously, each twisted pair need only transmit one-third (⅓) of the 100 Mbit/sec, or 33 Mbit/sec. By using the 8B6T coding, which converts the 8-bit binary code (a byte) into a 6-bit ternary code, the symbol rate on each twisted pair will be further reduced to six-eighths ({fraction (6/8)}) of the binary rate. The symbol rate of 100BASE-T4 is then brought down to 25 MHz, resulting in more reliable transmission over the conventional medium of twisted pair.
Though the use of multiple clock-data channels allows far greater speed of transmission, it creates additional complications in recovering and synchronizing the multiple received clock-data channels. Since there are unknown (and often random) delays on each channel (or on each twisted pair in the case of 100BASE-T4 Ethernet), a dedicated Clock-DATA recovering mechanism is required for each channel. Within each channel the recovered data will have a predictable relationship to the recovered clock. However, across the number of channels, the clock-data pairs will have unknown (and often random) phase delays between them. For proper data processing, the multiple streams of data must be synchronized to a single clock, or aligned. This is commonly called Multiple Receive Clock-DATA Channel Alignment.
Prior art Multiple Receive Clock-DATA Channel Alignment devices typically involve complicated Phase-Lock-Loops (PLLs) with either multiple phase clock outputs or a precision delay line with selectable fine time steps.
In prior art PLL designs with multiple phase clock outputs, such as that shown in
FIG. 1
, only one PLL will be used to lock onto the various incoming clock-data pairs. This main PLL will have a number of clock taps (or small increments). A complicated digital PLL algorithm will select one of the many different phase clock taps to be the “recovering clocks ” for each data channel. Then, the recovering clock will be continually modified by the algorithm to account for small changes in phase delay over time.
Other prior art PLL designs, such as the one depicted in
FIG. 2
, (as presented to the IEEE 802.3 Higher Speed Study Group, Irvine, Calif., Sep. 1993; use one main phase locked loop for one of the data channels. Timing recovery clocks for the rest of the channels are then generated from the main PLL clock. A multi-tapped analog precision delay line positioned after the main PLL clock will generate many different delayed clock signals, one at each tap. Depending on the incoming data stream transition edges and the clock picking algorithms, other channels will select recovering clocks from the analog precision delay chain. This type of design requires both complicated digital PLL circuits and precise analog delay chains.
In either typical PLL design there will necessarily be an algorithm (or algorithms) to: (1) select a recovered clock as a reference; (2) determine the phase differences between the reference clock and the other clocks; and (3) correct each of the non-reference data channels by the amount of their phase difference, thus synchronizing them to the reference clock.
The typical prior art Multiple Receive Clock-DATA Recovery Channel Alignment devices, as embodied by the PLL's described above, have several limitations. First, it is relatively difficult to design a precise clock-data recovery circuit because precision is limited by the number of taps of clocks available, how well the precision delay circuit is designed, or both. This presents an unpleasant tradeoff between alignment precision and circuit cost.
A second limitation concerns the many systems where the signaling is not continuous, such as Ethernet. In Ethernet systems, data travels in sets or groups, generally known as packets or frames; data packets may (and will) arrive unpredictably. In each data packet, a preamble will precede the data string to identify the data. The primary aligning PLL will do the initial lock-in (a zero phase start) during the very short preamble period of every data packet. However, the channels must also be synchronized during the same short preamble period. Since the synchronization process will be implemented on only a few clock edges, large jitters (unexpected changes in signal transmission) during the preamble may cause receiving errors late in the packet.
A third major limitation is the complexity and potential instability of the device. The digital circuit implementing the algorithm that selects the reference clock is highly complex. The algorithm must initially assume the reference clock is not moving. After selecting the recovering clock for the other
Dreyer Stephen F.
Jin Robert X.
West Eric T.
Gossage Glenn
LSI Logic Cororation
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