Silicon-germanium BiCMOS on SOI

Details Silicon-germanium BiCMOS on SOI Silicon-germanium BiCMOS on SOI

2001-01-24

2001-09-11

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S200000, C257S204000, C257S273000, C257S274000, C257S350000, C257S370000, C257S378000, C257S506000, C257S510000, C257S556000

Reexamination Certificate

active

06288427

ABSTRACT:

TECHNICAL FIELD
The field of the invention is silicon on insulator (SOI) integrated circuits incorporating BiCMOS circuitry.
BACKGROUND OF THE INVENTION
SiGe (silicon-germanium alloy) heterojunction bipolar transistors (HBTS) integrated with standard silicon CMOS forming the so-called SiGe BiCMOS circuits have been developed for analog/mixed signal applications in high-speed wireless and wired network communications. In SiGe BiCMOS, the base layer of the HBT is formed from SiGe alloy, different from conventional Si-only bipolar transistors which have a silicon base. Because of the narrow bandgap of SiGe alloy compared with the bandgap of the silicon emitter, the base layer can be highly doped to reduce the parasitic resistance without sacrificing the emitter efficiency. As a result, SiGe HBTs exhibit higher response frequency and higher gain as compared to the Si counterpart.
A major development in the silicon CMOS technology is the use of silicon-on-insulator (SOI) substrates which are now available commercially.
The integration of BiCMOS with SOI circuits opens another regime of high performance circuits also having low power consumption. Various integration schemes have been proposed previously; e.g. in U.S. Pat. No. 5,587,599 “Bipolar transistor and manufacturing method”, which disclosed a CMOS compatible bipolar transistor on an SOI substrate.
Some other prior publications such as S. Parke, et al., “A versatile SOI BiCMOS technology with complementary lateral BJT's,” IEEE IEDM 92, 453-456 (1992), also provided similar schemes.
For technologies utilizing the shallow trench isolation and planarization approach, the integration of SOI with SiGe BiCMOS suffers from the problem of processing compatibility. For partially depleted SOI silicon CMOS, the thin silicon film on top of the buried oxide should be about 0.1 &mgr;m to 0.2 &mgr;m thick, whereas the thickness of the silicon collector in the SiGe HBT (underneath the SiGe base layer) should be about 0.5 &mgr;m, substantially thicker than the CMOS silicon.
It is therefore the objective of the present disclosure to provide an integration scheme to fabricate SiGe HBT on a partially depleted silicon SOI CMOS circuits.
SUMMARY OF THE INVENTION
The invention relates to an integrated BiCMOS circuits on SOI, in which the bipolar transistors are formed with a silicon-germanium (SiGe) alloy base and an epitaxial silicon collector. The collector thickness is much thicker than the Si device layer in the SOI wafer.
An optional feature of the invention is the use of selective implantation of oxygen atoms for the buried oxide layer so that some or all of the bipolar transistors may be separated from the SOI region.
A feature of the invention is the use of shallow trench isolation on two levels—in the device layer to isolate the CMOS devices, and in the epitaxial silicon collector layer to provide isolation between base and collector junctions within one HBT device, as well as isolation between different devices.
An added feature of using the shallow trench is the complete isolation of bipolar device from the substrate by etching the shallow trench between devices down to the buried oxide. This eliminates the costly use of deep trench isolation to reduce device coupling to the substrate in the prior art.


REFERENCES:
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patent: 5102809 (1992-04-01), Eklund et al.
patent: 5164326 (1992-11-01), Foerstner
patent: 5182225 (1993-01-01), Matthews
patent: 5593915 (1997-01-01), Ohoka
patent: 5952695 (1999-09-01), Ellis-Monaghan et al.
patent: 02185061-A (1990-07-01), None

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