Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-12-17
2001-08-21
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06279129
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates, in general, to a configuration of memory cells and to a method of checking the operation of memory cells.
Integrated memories have memory cells that can store data. This is usually digital data, in other words, the logic states “0” and “1”. After a memory has been manufactured, it is necessary to check the operation of the memory and hence of the individual memory cells. It is customary practice to write test data to each individual memory cell and to read out this test data. To determine whether there is an operational fault, the test data that has been written in is compared with the test data that has been read out.
The following description illustrates how a simple operational check may be performed. First, data in the form of zeros are written to all of the memory cells in the integrated memory and are then read out. By comparing the data read out from each memory cell with the written data item “zero”, operational errors can be detected. Subsequently, a logic one is similarly written to all of the memory cells and is read out. The comparison described above takes place again for each memory cell, but now using the data item “one”. If an error is detected by at least one of the comparisons for a particular memory cell, it is regarded as faulty.
In addition to the simple case outlined, in which all logic zeros and all logic ones are respectively successively written to the memory cells and are read out again, more complicated test patterns can also be written to the memory.
To increase the yield in memory production, it is known to provide redundant rows and redundant columns of memory cells that can be used, dependent upon test results, to replace rows and columns having faulty memory cells. They are activated by an appropriate programming technique, for example using laser fuses, such that when the appropriate row or column address is applied, one of the redundant rows or columns is addressed instead of the row or column having the faulty memory cell or cells.
The operational check described above requires the transmission of large quantities of data. This includes the transmission of the data read out of the memory cells to an appropriate test facility performing the check and includes the data obtained from comparing the original test data with the data that has been read out. One factor limiting the potential data rate is the number of available connections in the memory. In particular, if the memory is a memory core situated as a so-called “embedded memory” together with other circuit components, such as a processor, on a common integrated circuit, this common integrated circuit has a small number of external connections that can be used to directly access the memory from outside of the integrated circuit. In extreme cases the common integrated circuit may not have any external connections that can be used to directly access the memory.
To get around the problem caused by the bottleneck of having only a few available connections, it is known practice, in embedded memories, to provide a test circuit with the memory on the integrated circuit. This test circuit can be a hardwired logic unit or a controller that independently carries out the desired operational check (i.e., writing the original test data to the memory cells, reading the data from the memory cells and comparing the data read out with the original test data) and supplies an appropriate result signal external to the integrated circuit if operational errors occur. However, the addresses of the faulty memory cells cannot be determined from outside of the integrated circuit. Such a setup is also called a “built-in self-test” (BIST).
To perform the operational check described, the test circuit generally has an appropriate memory that can store the test results.
U.S. Pat. No. 5,073,891 teaches a method and an apparatus for checking the operation of memory cells, in which the memory is divided into two groups (partitions) that are successively checked. While one group is being checked the other group is being used for other purposes.
U.S. Pat. No. 4,654,847 teaches an apparatus for automatically correcting erroneous data. Data errors are detected in a main memory. If these are single-bit errors, when the errors are read out, they are eliminated by an error correction unit. If multiple-bit errors occur, the address, the position, and the correct value of the respective data item are stored in an additional memory, that is smaller than the main memory.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of checking the operation of memory cells and an electronic circuit for performing the method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of checking the operation of memory cells. A first group of memory cells and a second group of memory cells are provided. The first group of memory cells is tested and a first set of test results is obtained, and the first set of test results is stored in the second group of memory cells. The first set of test results is read from the second group of memory cells. The second group of memory cells is tested and a second set of test results is obtained. The second set of test results is stored in the first group of memory cells. The method allows a test device to be provided that does not have memory. The complexity of the test device is therefore advantageously reduced.
In accordance with another feature of the invention, the memory cells of the two groups are component parts of a common memory or memory configuration, and temporary storage takes place in the memory cells of the second group before the test results are output from the memory. Since the memory cells of the first group are tested before test results are output to a device external to the common memory, the time when the test results are output is advantageously independent of the time during which they are produced. This means that the operational check can be performed more quickly, because it is performed independently of the delay that occurs due to the bottleneck of test results that are transmitted through external connections to a device that is not a part of the common memory.
A further advantage is that storing the test results in the memory configuration allows the temporarily stored test results to be evaluated before they are read out to outside of the memory. This allows the test results to be compressed by, for example, only outputting the addresses of faulty memory cells to outside of the memory configuration.
In accordance with an added feature of the invention, the stored test results are used to perform a redundancy analysis on the tested memory cells. Only the results of the redundancy analysis, namely the addresses of memory cell rows and columns that are to be replaced by redundant rows and redundant columns of memory cells are transmitted to outside of the memory configuration. This provides an advantage that the onchip redundancy analysis also compresses the test results, which are then output to outside of the memory configuration, not in their entirety, but merely in the reduced form of the result of the redundancy analysis. The quantity of data to be transmitted is thus significantly reduced. The result of the redundancy analysis transmitted to outside of the memory configuration can be used directly for appropriately programming the redundant rows and/or columns of the memory configuration using an appropriate external programming circuit. For example, a laser can be used to melt separable connections.
In accordance with an additional feature of the invention, the stored test results are read out of the memory cells of the second group and the memory cells of the second group are then tested. The test results from the memory cells of the second group are then temporarily stored in the memory cells of the first group. This allows all of the memory cells in the memory configuration to be checked in two successive phases
McConnell Roderick
Richter Detlev
Chung Phung M.
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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