Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-08-18
2001-05-29
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C709S241000, C714S012000
Reexamination Certificate
active
06240152
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to circuits for controlling clock signals in microprocessors. More particularly, this invention relates to a circuit that rapidly changes between normal and reduced power clock frequency operating modes while maintaining phase lock.
BACKGROUND OF THE INVENTION
Microprocessors are operated in response to a system clock. The increase in microprocessor speeds and the simultaneous reduction in power supply voltages impose restrictions on the design of microprocessor system clocks. In addition to microprocessor speed and power supply constraints, there is a demand for increased system clock frequency shifting flexibility. The frequency of the system clock of a microprocessor may be shifted for testing purposes or to preserve power.
Phase-locked loop circuits are widely used in electronic systems. These circuits are used to generate an accurate replica of an incoming signal. For example, in a computer, a phase-locked loop is used by a microprocessor to generate an on-chip clock signal from an off-chip clock signal.
To conserve power, it is desirable to reduce a microprocessors clock frequency when it is not being used. In conventional computer systems phase-locked loop circuits lose phase lock when the microprocessor clock frequency is changed. This increases the amount of time required to switch between a power saving mode and normal operation. In addition, the loss of phase lock may cause a signal to violate timing requirements and thereby create a metastable state which can cause the microprocessor to malfunction.
In view of these and other problems of conventional microprocessor phase-locked loop systems, it would be highly desirable to provide a phase-locked loop system that maintains phase lock when clock frequencies are changed, enables rapid switching between normal operating modes and power saving modes, and provides deterministic operation so as to avoid metastable states.
SUMMARY OF THE INVENTION
The invention is a frequency mode switching system for a microprocessor that maintains phase lock in a phase-locked loop while switching clock frequencies. The frequency mode switching system receives a system clock signal at an input buffer. A first frequency shifter divides the system clock by a division ratio specified by the CPU, to produce a reference signal. The reference signal is coupled to a phase-locked loop (PLL) circuit. The phase-locked loop circuit has a voltage controlled oscillator (VCO) that outputs a signal at a normal operating frequency to a third frequency shifter. The third frequency shifter divides down the VCO output signal to produce a CPU clock signal. After passing through the CPU clock distribution network the CPU clock signal is coupled to a second frequency shifter which divides the CPU clock signal and outputs a feedback signal to the PLL circuit. The PLL circuit maintains phase and frequency lock between the feedback signal and the reference signal.
When the CPU provides a command signal to at least one of the frequency shifter circuits to change its frequency division ratio, the signal is detected by a comparator which compares the current frequency division ratio of each of the frequency shifters to the CPU frequency command signal for each frequency shifter. The comparator outputs a reload signal to a synchronizer circuit. The synchronizer circuit aligns the reload signal to the VCO output signal and selects the appropriate VCO output cycles that the division ratio of each of the frequency shifters should be updated on. To maintain phase-lock the third frequency shifter division ratio is updated first. The third frequency shifter division ratio update is also timed so that the start of the first new clock frequency cycle is aligned with the start of a reference clock cycle. The first and second frequency shifters are then updated after a delay based on the delay of the CPU clock distribution network to enable the PLL to maintain phase lock between the reference signal and feedback signal inputs. The invention thus maintains phase lock while changing clock frequency operating modes which provides deterministic operation and avoids metastability. The invention further provides for rapid switching from a normal operating mode to a reduced frequency mode and back to normal. For example, one embodiment can switch from a normal operating mode to a reduced frequency mode and back to normal in 4 CPU clock cycles.
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Chin Stephen
Fan Chieh M.
Pennie & Edmonds LLP
Sun Microsystems Inc.
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