Multiple clock rate test apparatus for testing digital systems

Details Multiple clock rate test apparatus for testing digital systems Multiple clock rate test apparatus for testing digital systems

1992-03-26

1994-09-20

Beausoliel, Jr., Robert W.

Excavating

371 27, A04B 1700, G01R 3128

Patent

active

053495870

ABSTRACT:
In methods and apparatus for testing a digital system, scannable memory elements of the digital system are configured in a scan mode in which the memory elements are connected to define a plurality of scan chains. A test stimulus pattern is clocked into each of the scan chains at a respective clock rate, at least two of the clock rates being different from one another. The memory elements of each scan chain are then configured in a normal operation mode in which the memory elements are interconnected by the combinational network for at least one clock cycle at a highest of the respective clock rates. The memory elements are then reconfigured in the scan mode, and a test response pattern is clocked out of each of the scan chains at its respective clock rate. The methods and apparatus are particularly useful for testing digital systems such as digital integrated circuits in which different memory elements are clocked at different rates during normal operation.

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"Self-Testing of Multichip Logic Modules", Paul H. Bardell and William H. McAnney, IBM Corp., 1982 IEEE Test Conference.

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