Memory testing apparatus

Details Memory testing apparatus Memory testing apparatus

1999-02-19

1999-08-31

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

365200, G11C 700

Patent

active

059462507

ABSTRACT:
There is provided a memory testing apparatus having, for a high speed device testing, a failure data display controller for memory test including a display apparatus for displaying positions of failure memory cells based on failure data obtained by testing of a memory.
After the test is completed, the failure data stored in a failure memory for storing failure data are transferred to a failure buffer memory for temporarily storing failure data provided in the failure data display controller. The failure data stored in the failure buffer memory are converted and transferred to the display apparatus. During the time period when the next device is being tested, the failure cell positions of the previously tested device are displayed on the display apparatus.

REFERENCES:
patent: 5835429 (1998-11-01), Schwarz
patent: 5859804 (1999-01-01), Hedberg et al.

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