Semiconductor memory device having a memory cell region and a pe

Details Semiconductor memory device having a memory cell region and a pe Semiconductor memory device having a memory cell region and a pe

1997-09-04

1999-08-31

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257393, 257368, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

059457155

ABSTRACT:
LOCOS isolation is used for isolation between wells in a memory cell part, and an isolation width is reduced, so that a degree of integration of memory cells is improved in a semiconductor memory device. At the memory cell part in the semiconductor memory device, depths of a well region and source/drain regions are reduced, so that a width of an element isolating insulation film are reduced.

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Fumitomo Matsuoka et al, High-density Full-CMOS SRAM Cell Technology with a Deep Sub-Micron Spacing between nMOS and pMOSEFET, IEICE Trans, Electron., vol. E77-C, No. 8, Aug. 1994, pp. 1385-1394.

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