Semiconductor memory with improved test mode

Details Semiconductor memory with improved test mode Semiconductor memory with improved test mode

1993-06-02

1994-05-10

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

36518905, 36523006, 36523008, G11C 1300

Patent

active

053114736

ABSTRACT:
An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals. The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.

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