Multi-way cache expansion circuit architecture

Details Multi-way cache expansion circuit architecture Multi-way cache expansion circuit architecture

1995-11-17

1998-12-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711129, 711136, 711160, G06F 1200, G11C 1300

Patent

active

058453172

ABSTRACT:
An expandable-set, tag, cache circuit for use with a data cache memory comprises a tag memory divided into a first set and a second set for storing, under a single address location, first and second tag fields representative of first and second data, respectively. The tag memory also stores first and second signals representative of which of the sets is the least recently used. A comparator is responsive to a tag field of an address representative of requested data as well as to a first tag field output from the tag memory for producing an output signal indicative of a match therebetween. A second comparator is responsive to the same tag field of the address and to a second tag field output from the tag memory for producing an output signal indicative of a match therebetween. A first logic gate is responsive to the first and second comparators for producing an output signal indicative of the availability of the requested data in the data cache memory. A second logic gate is responsive to the first logic gate and an external signal. A first write driver is enabled by the output of the first logic gate and is responsive to the output of the first comparator for controlling the state of the first signal. A second write driver is enabled by the output of the second logic gate and is responsive the to external signal for controlling the state of the second signal.

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