CMOS buffer with controlled slew rate

Details CMOS buffer with controlled slew rate CMOS buffer with controlled slew rate

1995-06-05

1997-04-08

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 27, 326 83, H03K 1716, H03K 190948

Patent

active

056191472

ABSTRACT:
A method and apparatus for a circuit physically realizing a CMOS buffer with a controlled slew rate at the output and using no additional standby power to achieve the slew rate control is described. A feedback path from the output is coupled to transistors comprising a differential pair, the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback path to control the high-to-low and low-to high transition rate of the output. The circuit of the invention allows a system designer to construct a buffer for driving a bus with excellent on chip and bus signal noise characteristics using standard digital CMOS technology and having excellent standby and active power characteristics. An open drain buffer and a push-pull buffer are described. An integrated circuit implementing application logic coupled to input/output and output buffers embodying this circuit is disclosed. Other embodiments are also disclosed.

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